Device and method for information processing
AssigneeFujitsu Limited
InventorsHiroshi Okano, Fumihiko Hayakawa
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Abstract
In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to seventh selectors appropriately select either the first address or the second address, and supply the selected address to first to seventh memory areas, respectively. An eighth memory area is supplied with the first address.
Claims20
An information processing device provided with a memory consisting of N memory areas with a M-bit width and having a M×N-bit write width where M and N are natural numbers, the information processing device comprising:
- a first register that stores first data to generate addresses;
- a second register that stores second data to generate addresses;
- a third register that stores write sizes;
- a first address adder that generates a first address, based on the data stored in the first register and the data stored in the second register;
- a second address adder that generates a second address by adding N to the first address;
- a write control circuit that generates write control signals for the N memory areas, based on the first address and the write sizes;
- (N−1) selectors that select either the first address or the second address according to the first address;
- the (N−1) memory areas of the first to the (N−1)th memory areas into which data is written, based on the addresses supplied from the selectors and the write control signals;
- and
- the Nth memory area into which data is written, based on the first address and the write control signals.
An information processing device provided with a memory consisting of N memory areas with a M-bit width and having a M×N-bit write width where M and N are natural numbers, the information processing device comprising:
- a first register that stores first data to generate addresses;
- a second register that stores second data to generate addresses;
- a third register that stores write sizes;
- a first address adder that generates a first address, based on the data stored in the first register and the data stored in the second register;
- a second address adder that generates a second address by adding N to the first address;
- (N−1) selectors that select either the first address or the second address according to the first address;
- the (N−1) memory areas of the first to the (N−1)th memory areas from which data is read, based on the addresses supplied from the selectors;
- and
- the Nth memory area from which data is read, based on the first address.
An information processing device provided with a memory consisting of N memory areas with a M-bit width and having a M×N-bit write width where M and N are natural numbers, the information processing device comprising:
- a first register that stores first data to generate addresses;
- a second register that stores second data to generate addresses;
- a third register that stores write sizes;
- a first address adder that generates a first address, based on the data stored in the first register and the data stored in the second register;
- a second address adder that generates a second address by adding N to the first address;
- a write control circuit that generates write control signals for the N memory areas, based on the first address and the write sizes;
- (N−1) selectors that select either the first address or the second address according to the first address;
- the (N−1) memory areas of the first to the (N−1)th memory areas into which data is written based on the addresses supplied from the selectors and the write control signals, or from which data is read based on the addresses supplied from the selectors;
- and
- the Nth memory area into which data is written based on the first address and the write control signals, or from which data is read based on the first address.
An information processing method in an information processing device provided with a memory consisting of N memory areas with a M-bit width and having a M×N-bit write width where M and N are natural numbers, the information processing method comprising steps of:
- inputting first data and second data to generate addresses, and write sizes;
- generating a first address based on the first data and the second data;
- generating a second address by adding N to the first address;
- generating write control signals for N of the memory areas based on the first address and the write sizes;
- selecting either the first address or the second address according to the first address;
- and
- writing data into the (N−1) memory areas of the first to the (N−1)th memory areas based on the address selected in the selection step and the write control signals, and writing data into the Nth memory area based on the first address and the write control signals.
An information processing method in an information processing device provided with a memory consisting of N memory areas with a M-bit width and having a M×N-bit write width where M and N are natural numbers, the information processing method comprising steps of:
- inputting first data and second data to generate addresses, and write sizes;
- generating a first address based on the first data and the second data;
- generating a second address by adding N to the first address;
- generating write control signals for N of the memory areas based on the first address and the write sizes;
- selecting either the first address or the second address according to the first address;
- writing data into the (N−1) memory areas of the first to the (N−1)th memory areas based on the address selected in the selection step and the write control signals, and writing data into the Nth memory area based on the first address and the write control signals;
- and
- reading data from the (N−1) memory areas of the first to the (N−1)th memory areas based on the address selected in the selection step, and reading data from the Nth memory area based on the first address.
Dependencies are inferred from the claim text.