Carry generation in address calculation

A carry generation circuit for generating a carry of a sum of a first and second numbers, the carry generation circuit comprising:

• a plurality of inputs configured to receive the first and second numbers;
• and
• a generate and propagate term generation circuit coupled to the inputs and configured to (a) generate propagate terms, generate terms, combined generate terms, and combined propagate terms from the first and second numbers, and (b) generate the carry from the propagate terms, the generate terms, the combined generate terms, and the combined propagate terms.

A method for generating a first propagate term from a first and second operand bits, the method comprising:

• providing at least a first and second gates having a dotted output;
• and
• passing the first and second operand bits through the first and second gates, respectively, to the dotted output so as to generate the first propagate term at the doffed output.

A propagate term generation circuit for generating a first propagate term from a first and second operand bits, the propagate term generation circuit comprising:

• at least a first and second gates having a dotted output wherein the first and second gates are configured to receive the first and second operand bits, respectively, and generate the first propagate term at the dotted output.

A generate term generation circuit for generating a first generate term from a first bit and a second bit of a plurality of N bits, the generate term generation circuit comprising:

• N−1 combining gates having a dotted output, the N−1 combining gates being configured to receive the first bit as their first inputs, and receive one-for-one the remaining N−1 bits including the second bit as their second inputs;
• wherein a first combining gate of the N−1 combining gates combines the first and second bits to generate the first generate term.

A method for generating a carry of a sum of a first and second N-bit numbers, the method comprising:

• adding, with an adder, M most significant bits of the first and second numbers to generate the carry, M being at least one but less than N.

A carry generation circuit for generating a carry of a sum of a first and second N-bit numbers, the carry generation circuit comprising:

• an addition circuit configured to receive M most significant bits of the first and second numbers and add the M most significant bits of the first and second numbers to generate the carry, M being at least one but less than N.