US 2003/0126397 A1 · Configurable addressing apparatus

Abstract

Apparatus for addressing a data memory (21), with the apparatus (1) having: an instruction register (2) for buffer-storing a program instruction, which comprises an instruction opcode, a memory configuration selection pointer (2b) for selection of a memory configuration register field, configuration bits (2c) and offset address bits (2d), a memory configuration register (11) which comprises a number of memory configuration register fields (11-i) which store different mapping instructions for generation of a data memory address in the data memory (21), a number of data memory segment registers (14) which each store the most significant address bits of a start address for a data memory segment, at least one additional data memory segment register (16) which stores the most significant address bits of a start address for a data memory segment, a switching mechanism (9) which reads the mapping instruction from the selected memory configuration register field (11-i) as a function of the memory configuration selection pointer read from the instruction register (2), and, depending on the mapping instruction that is read, and as a function of the configuration bits (2c) read from the instruction register (2), composes the most significant address bits from a data memory segment register (14) or an additional data memory segment register (16) and from the configuration bits (2c) read from the instruction register (2), and writes the result to an address register (19) which buffer-stores a data memory address for addressing the data memory (21), with the least significant address bits of the address register (19) being taken from the offset address bits (2d) which are buffer-stored in the instruction register (2).

Claims8

Dependent claims

Apparatus for addressing a data memory (21), with the apparatus (1) having:

(a) an instruction register (2) for buffer-storing a program instruction, which
comprises an instruction opcode (2a), a memory configuration selection pointer (2b) for selection of a memory configuration register field, configuration bits (2c) and offset address bits (2d);
(b) a memory configuration register (11) which comprises a number of memory configuration register fields (11-i) which store different mapping instructions for generation of a data memory address in the data memory (21);
(c) a number of data memory segment registers (14) which each store the most significant address bits of a start address for a data memory segment, at least one additional data memory segment register (16) which stores the most significant address bits of a start address for a data memory segment,
(d) a switching mechanism (9) which reads the mapping instruction from the selected memory configuration register field (11-i) as a function of the memory configuration selection pointer (2b) read from the instruction register (2), and, depending on the mapping instruction that is read, interprets each individual bit of the configuration bits (2c) either as a selection bit or as an additional offset address bit, and composes the most significant address bits from the data memory segment register (14)/additional data memory segment register (16) selected by the selection bits and from the additional offset address bits, and writes the result to the most significant bit positions in an address register (19) which buffer-stores a data memory address for addressing the data memory (21),
with the least significant address bits of the address register (19) being taken from the offset address bits (2d) which are buffer-stored in the instruction register (2).

3 more elements

Dependencies are inferred from the claim text.

Configurable addressing apparatus

Life of this patent

Configurable addressing apparatus

Life of this patent

Abstract

Claims8