A method of controlling page mode access
AssigneeHitachi, Ltd.
InventorsSeiji Miura, Kazushige Ayukawa
Life of this patent
Estimating the term…
Abstract
A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
Claims24
A memory controller having a first mode and a second mode, wherein said first mode has a memory access with the output of a column address and without the output of a row address, and said second mode has a memory access having precharge control after the output of a row address and a column address, the mode being switched to said first mode in the case of a memory access with the output of a row address and a column address following the precharge control in said first mode.
A data processing system comprising:
- a central processing unit which puts out an address;
- a memory controller which is supplied with the address and adapted to operate in a first mode or a second mode;
- and
- a memory which is controlled by said memory controller,
- wherein the mode of said memory controller is switched from said first mode to said second mode in response to an event of access to a first page of said memory and a subsequent event of access to a second page which is different from the first page in said first mode.
A memory controller comprising:
- a plurality of input nodes where an address is inputted to;
- a first register circuit which stores the address inputted to said input nodes;
- a first comparator circuit comparing the address inputted to said input nodes with the address stored in said first register circuit;
- a second comparator circuit comparing the contents of a second register circuit with the output of said first register circuit;
- and
- a first circuit which is set in a first state or a second state depending on the output of said second comparator circuit.
A method of controlling a memory by a memory controller having a first mode and a second mode,
- wherein said memory comprises a plurality of word lines, data lines, and memory cells,
- wherein said memory is controlled to perform a precharge operation after a read access in said first mode,
- wherein said memory is controlled to receive a next access command without a precharge operation after a read access in said second mode,
- wherein said memory controller has a circuit comparing a first address inputted and the address previous to said first address to control the mode for access commands corresponding to an address inputted after said first address.
Dependencies are inferred from the claim text.