Memory arbiter with grace and ceiling periods and intelligent page gathering logic
AssigneeIntel Corporation
InventorsJosh B. Mastronarde, Aditya Sreenivas, Thomas A. Piazza
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Abstract
Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.
Claims36
A memory arbiter, comprising:
- a memory area;
- and
- a memory controller coupled to the memory area, wherein the memory controller is configured to receive memory requests and corresponding priorities from a microprocessor, and wherein the memory controller is configured to continue to service current lower priority requests for a predefined period if an incoming higher priority request is directed to a same page of memory as the current lower priority requests.
A method for servicing data in a computer system, comprising:
- receiving a first memory request;
- servicing the first memory request;
- receiving a second memory request having a priority greater than the first memory request;
- and
- continuing to process the first memory request for a predefined period if the second memory request is directed to a same page of memory as the first memory request.
A computer system, comprising:
- a processor to initiate higher and lower priority memory requests;
- a memory area;
- and
- a memory controller coupled to the memory area, wherein the memory controller is configured to receive memory requests and corresponding priorities from the processor, and wherein the memory controller is configured to continue to service current lower priority requests for a predefined period if an incoming higher priority request is directed to a same page of memory as the current lower priority requests.
A machine readable medium having stored therein a plurality of machine readable instructions executable by processor to service data, comprising:
- instructions to receive a first memory request;
- instructions to service the first memory request;
- instructions to receive a second memory request having a priority greater than the first memory request;
- and
- instructions to continue to process the first memory request for a predefined period if the second memory request is directed to a same page of memory as the first memory request.
A memory arbiter, comprising:
- a memory area;
- and
- a memory controller coupled to the memory area, wherein the memory controller is configured to receive memory requests and corresponding priorities from a microprocessor, and wherein the memory controller is configured to interrupt servicing of higher priority requests after a predefined number are processed to process lower priority requests for a predefined period of time.
A method to service data in a computer system, comprising:
- receiving and servicing a plurality of high priority memory requests;
- receiving one or more memory requests having lower priority than the plurality of higher priority memory requests;
- and
- interrupting servicing of higher priority requests after a predefined number is processed to process one or more lower priority requests for a predefined period of time.
A computer system, comprising:
- a processor for initiating a higher and lower priority memory requests;
- a memory area;
- and
- a memory controller coupled to the memory area, wherein the memory controller is configured to receive memory requests and corresponding priorities from the processor, and wherein the memory controller is configured to interrupt servicing of higher priority requests after a predefined number is processed to process one or more lower priority requests for a predefined period of time.
A machine readable medium having stored therein a plurality of machine readable instructions executable by a processor to service data, comprising:
- instructions to receive and service a plurality of high priority memory requests;
- instructions to receive one or more memory requests having lower priority than the plurality of higher priority memory requests;
- and
- instructions to interrupt servicing of higher priority requests after a predefined number are processed to process one or more lower priority requests for a predefined period of time.
Dependencies are inferred from the claim text.