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US 2003/0126377 A1Published application
Method and apparatus for communicating between integrated circuits in a low power mode
AssigneeIntel Corporation
InventorsDoron Orenstien, Marcelo Yuffe
Life of this patent
Estimating the term…
Abstract
For one embodiment, a computer system includes both high power and low power buses coupling a processor to a controller. When the processor is in a high power mode, its cache is snooped by the controller via the high power bus. When the processor is in a low power mode, its cache is snooped by the controller via the low power bus.
Claims30
A computer system, comprising:
- a processor comprising a cache, a first bus interface and a second bus interface;
- and
- a controller to snoop the cache via the first bus interface during a first mode of operation and to snoop the cache via the second bus interface during a second mode of operation.
A computer system, comprising:
- a high power bus;
- a low power bus that is narrower than the high power bus and includes a clock signal line for source-synchronous operation;
- a processor comprising a cache, a high power bus interface coupled to the high power bus and a low power bus interface coupled to the low power bus;
- and
- a controller to communicate with the processor via the high power bus during a high power mode of operation and to communicate with the processor via the low power bus during a low power mode of operation.
2 more elements
An integrated circuit comprising:
- a high power bus interface through which a memory region may be snooped during a high power mode of operation;
- and
- a low power bus interface through which the memory region may be snooped during a low power mode of operation.
A method of accessing a cache comprising:
- snooping a cache via a high power bus during a high power mode of operation;
- transitioning to a low power mode of operation;
- and
- snooping the cache via a low power bus during a low power mode of operation.
1 more element
Dependencies are inferred from the claim text.