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US 2003/0126376 A1Published application
Cache coherency arrangement to enhance inbound bandwidth
AssigneeIntel Corporation
InventorsRobert G. Blankenship, Matthew A. Lambert, Tony S. Rand
Life of this patent
Estimating the term…
Abstract
A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.
Claims30
An apparatus, comprising:
- a snoop filter to determine a conflict associated with an ownership of a memory line;
- a hub interface coupled with said snoop filter to maintain a transaction order for an upbound transaction associated with the ownership, from an input-output interface, and to determine a coherency state for the upbound transaction based upon the conflict and the transaction order, to take the ownership from the upbound transaction;
- and
- an upbound path coupled with said hub interface to transmit the upbound transaction to an unordered interface.
1 more element
A method, comprising:
- maintaining a transaction order for an upbound transaction based upon an ordering of an input-output interface to transmit the upbound transaction to an unordered interface;
- determining a conflict associated with an ownership of a memory line by the upbound transaction;
- and
- determining a coherency state for the upbound transaction based upon the conflict and the transaction order, to take the ownership from the upbound transaction.
1 more element
A system, comprising:
- a snoop filter to determine a conflict associated with an ownership of a memory line;
- a hub interface coupled with said snoop filter to maintain a transaction order for an upbound transaction associated with the ownership, from an input-output interface, and to determine a coherency state for the upbound transaction based upon the conflict and the transaction order, to take the ownership from the upbound transaction;
- an upbound path coupled with said hub interface to transmit the upbound transaction to an unordered interface;
- a memory circuit coupled with said upbound path to store data on a memory line associated with the upbound transaction;
- and
- a input-output device coupled with said hub interface to transmit the upbound transaction to access said memory circuit.
3 more elements
A machine-readable medium containing instructions, which when executed by a machine, cause said machine to perform operations, comprising:
- maintaining a transaction order for an upbound transaction based upon an ordering of an input-output interface to transmit the upbound transaction to an unordered interface;
- determining a conflict associated with an ownership of a memory line by the upbound transaction;
- and
- determining a coherency state for the upbound transaction based upon the conflict and the transaction order, to take the ownership from the upbound transaction.
1 more element
Dependencies are inferred from the claim text.