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US 2003/0126373 A1Published application
Distributed memory module cache writeback
AssigneeIntel Corporation
InventorHoward S. David
Life of this patent
Estimating the term…
Abstract
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. Writes to a memory module are stored in the data cache which allows the writes to be postponed until the DRAM on the memory module is not busy.
Claims15
An apparatus, comprising:
- an array of tag address storage locations;
- and
- a command sequencer and serializer unit coupled to the array of tag address storage locations, the command sequencer and serializer unit to control a data cache associated with a memory module, the command sequencer and serializer unit to cause a current line of data to be written from the command sequencer and serializer unit to the data cache.
An apparatus, comprising:
- at least one memory device;
- and
- a data cache coupled to the memory device, the data cache controlled by a plurality of commands delivered by a memory controller component over a memory bus, the memory controller component including an array of tag address storage locations, the memory controller writing a current line of data to the data cache.
A system, comprising:
- a processor;
- a memory controller coupled to the processor, the memory controller including
- an array of tag address storage locations, and
- a command sequencer and serializer unit coupled to the array of tag address storage locations;
- and
- a memory module coupled to the memory controller, the memory module including
- at least one memory device, and
- a data cache coupled to the memory device, the data cache controlled by a
- plurality of commands delivered by the memory controller, the memory controller writing a current line of data to the data cache.
6 more elements
A method, comprising:
- writing a current line of data from a memory controller to a data cache located on a memory module;
- evicting a previous line of data from the data cache to an eviction buffer located on the memory module;
- and
- writing the previous line of data from the eviction buffer to a memory device on the memory module when the memory device is not busy.
1 more element
Dependencies are inferred from the claim text.