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US 2003/0126372 A1Published application
Cache coherency arrangement to enhance inbound bandwidth
OwnerTony S. Randinventor
Life of this patent
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Abstract
A cache coherency arrangement with support for pre-fetching ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing and address matching to reduce transaction latency and prevent deadlock and/or starvation. Several embodiments may also comprise cache to reduce transaction latency and logic to populate the cache.
Claims30
An apparatus, comprising:
- an input-output interface to receive a first transaction associated with a first address;
- an address queue coupled with said input-output interface to store a second address of a pending transaction;
- address logic circuitry coupled with said address queue to compare the first address against the second address;
- and
- ownership pre-fetch circuitry coupled with said address logic circuitry to initiate a request for an ownership of a first memory content associated with the first address for the first transaction unless the first address is substantially equivalent to the second address.
2 more elements
A method, comprising:
- receiving a first transaction from an ordered interface;
- comparing a first address associated with the first transaction against a second address in an address queue, wherein the second address is associated with a second transaction;
- and
- pre-fetching ownership of a memory content associated with the first address, wherein the first address is different from the second address.
1 more element
A system, comprising:
- an input-output interface to receive a first transaction associated with a first address;
- an address queue coupled with said input-output interface to store a second address of a pending transaction;
- address logic circuitry coupled with said address queue to compare the first address against the second address;
- ownership pre-fetch circuitry coupled with said address logic circuitry to initiate a request for an ownership of a first memory content associated with the first address for the first transaction, wherein the first address is different from the second address;
- a transaction queue coupled with said input-output interface to maintain a transaction order for the pending transaction;
- and
- a memory device coupled with said transaction queue to respond to the pending transaction.
4 more elements
A machine-readable medium containing instructions, which when executed by a machine, cause said machine to perform operations, comprising:
- receiving a first transaction from an ordered interface;
- comparing a first address associated with the first transaction against a second address in an address queue, wherein the second address is associated with a second transaction;
- and
- pre-fetching ownership of a memory content associated with the first address, wherein the first address is different from the second address.
1 more element
Dependencies are inferred from the claim text.