System and method for performing page table walks on speculative software prefetch operations

A method comprising:

• determining whether a linear address specified by a micro-operation (micro-op) is contained within a translation-lookaside buffer (TLB);
• performing page table walk if a TLB miss occurs;
• determining whether a fault has occurred;
• if a fault is detected, then
• determining whether the faulting micro-op relates to a non-prefetch memory access operation or a prefetch memory access operation,
• updating a first fault register if the faulting micro-op relates to a non-prefetch memory access operation, and
• updating a second fault register if the faulting micro-op relates to a prefetch memory access operation.

A processor comprising:

• a translation-lookaside buffer (TLB) to perform linear address translation operation associated with a linear address specified by a micro-operation (micro-op);
• a page miss handler to perform page table walk in response to a TLB miss;
• a first fault register to store information associated with a faulting micro-op relating to a non-prefetch memory access operation;
• and
• a second fault register to store information associated with a faulting micro-op relating to a prefetch memory access operation.