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US 2003/0126368 A1Published application
Distributed memory module cache tag look-up
AssigneeIntel Corporation
InventorHoward S. David
Life of this patent
Estimating the term…
Abstract
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. The tag look-ups are performed in parallel with the memory module decodes. This improves latency for cache hits without penalizing the latency for cache misses.
Claims18
An apparatus, comprising:
- a plurality of tag units, each tag unit including an array of tag address storage locations, the plurality of tag units to perform tag look-up operations;
- a memory module decode unit, the memory module decode unit to perform decode operations in parallel with the tag look-up operations;
- and
- a command sequencer and serializer unit coupled to the array of tag address storage locations, the command sequencer and serializer unit to control a plurality of data caches, each data cache associated with one of a plurality of memory modules.
1 more element
A system, comprising:
- a processor;
- a memory controller coupled to the processor, the memory controller including
- a plurality of tag units, each tag unit including an array of tag address
- storage locations, the plurality of tag units to perform tag look-up operations;
- a memory module decode unit, the memory module decode unit to perform
- decode operations in parallel with the tag look-up operations;
- and
- a command sequencer and serializer unit coupled to the array of tag address storage locations;
- and
- a plurality of memory modules coupled to the memory controller, each of the plurality of memory modules including
- a memory device, and
- a data cache coupled to the memory device, the data cache controlled by
- commands delivered by the memory controller.
10 more elements
A method, comprising:
- receiving a read request at a memory controller;
- performing a tag look-up within the memory controller to determine whether there is a cache hit for the read request;
- determining which of a plurality of memory modules is addressed by the read request, wherein performing a tag look-up and determining which of a plurality of memory modules is addressed by the read request occur in parallel;
- and
- fetching a line of cache data from a data cache located on one of the plurality of memory modules if the tag look-up indicates a cache hit.
2 more elements
Dependencies are inferred from the claim text.