Method for extending the local memory address space of a processor
AssigneeIntel Corporation
InventorsJuan G. Revilla, Ravi Kolagotla
Life of this patent
Estimating the term…
Abstract
A processor may include a local addressable memory, e.g., an SRAM, in parallel with a local cache at the highest level of the memory hierarchy, e.g., Level 1 (L1) memory. A local memory controller may handle accesses to L1 memory. The local memory controller may determine the page which includes the requested memory location and examine a page descriptor, e.g., an L1 SRAM bit, to determine if the page is in local memory. The local memory controller routes the access to the local addressable memory or the local cache depending on the state of the L1 SRAM bit.
Claims27
A method comprising:
- receiving a request for access to a memory location;
- identifying a memory block including the memory location;
- examining a local memory descriptor associated with said memory block;
- and
- accessing a local addressable memory in response to the local memory descriptor indicating that the memory block is in the local addressable memory.
A method comprising:
- receiving a request for access to a memory location;
- identifying a memory block including the memory location;
- and
- routing the request to one of a local addressable memory and a local cache in response to the state of a local memory descriptor associated with said memory block.
An apparatus comprising:
- an execution unit;
- a local addressable memory;
- a local cache;
- and
- a local memory controller operative to identifye a memory block including a memory location in response to receiving a request for access to said memory location from the execution unit and to route the request to one of the local addressable memory and the local cache in response to the state of a local memory descriptor associated with said memory block.
A system comprising:
- a processor including
- an execution unit,
- a local addressable memory,
- a local cache, and
- a local memory controller operative to identify a memory block including a memory location in response to receiving a request for access to said memory location from the execution unit and to route the request to one of the local addressable memory and the local cache in response to the state of a local memory descriptor associated with said memory block;
- and
- a USB (Universal Serial Bus) interface;
- and
- a system bus coupled to the processor and the USB interface.
An article comprising a machine-readable medium including machine-executable instructions, the instructions operative to cause a machine to:
- receive a request for access to a memory location;
- identify a memory block including the memory location;
- examine a local memory descriptor associated with said memory block;
- and
- access a local addressable memory in response to the local memory descriptor indicating that the memory block is in the local addressable memory.
An article comprising a machine-readable medium including machine-executable instructions, the instructions operative to cause a machine to:
- receive a request for access to a memory location;
- identify a memory block including the memory location;
- and
- route the request to one of a local addressable memory and a local cache in response to the state of a local memory descriptor associated with said memory block.
Dependencies are inferred from the claim text.