Back to results
US 2003/0126365 A1Published application
Transfer of cache lines on-chip between processing cores in a multi-core system
AssigneeIntel Corporation
InventorsSujat Jamil, Quinn W. Merrell, Cameron B. McNairy
Life of this patent
Estimating the term…
Abstract
Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific embodiments are described, using write buffers, fill buffers, and multiplexers, respectively, to achieve the on-chip transfer of data between dedicated caches.
Claims26
An apparatus, comprising:
- an integrated circuit including
- a first processor with a first dedicated cache;
- a second processor with a second dedicated cache;
- and
- control logic coupled to the first and second dedicated caches to transfer first data from the first dedicated cache to the second dedicated cache entirely within the integrated circuit.
2 more elements
A method, comprising:
- transferring first data from a first dedicated cache of a chip multi-processor to control logic in the chip multi-processor, entirely within the chip multiprocessor;
- and
- subsequently transferring the first data from the control logic to a second dedicated cache of the chip multi-processor, entirely within the chip multi-processor.
A system, comprising:
- a main memory,
- a chip multiprocessor coupled to the main memory and including:
- a first processor with a first dedicated cache;
- a second processor with a second dedicated cache;
- and
- control logic coupled to the first and second dedicated caches to transfer first data from the first dedicated cache to the second dedicated cache entirely within the chip multiprocessor.
3 more elements
A machine-readable medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:
- transferring data from a first dedicated cache in an integrated circuit to control logic in the integrated circuit, entirely within the integrated circuit;
- and
- subsequently transferring the data from the control logic to a second dedicated cache of the integrated circuit, entirely within the integrated circuit.
Dependencies are inferred from the claim text.