Arrangement and method for reducing the processing time of a data processing device
AssigneeFujitsu Siemens Computer GmbH
InventorNikolaus Demharter
Life of this patent
Estimating the term…
Abstract
The invention herein pertains to a data processing device (1) with a processor (2) and a memory (3). The memory (3) comprises a first memory sector (4) and a second memory sector (6), a first cache (5) being arrayed for the first memory sector (4) and a second cache (7) being arrayed for the second memory sector (6). It is the function of the second cache (7) that predetermined and selected sub-programs, interrupt vectors (8) and interrupt handlers (9), which are normally stored in the second memory sector (6), which is, for example, a ROM memory or a RAM memory, are saved in temporary storage in the second cache (7). It is an advantage that no displacement cycles take place in the second cache (7).
Claims10
Data processing device (1) with:
- a processor (2);
- a memory (3) connected to the processor (2) and having a first memory sector (4) and a second memory sector (6);
- a first cache (5) which images the first memory sector (4) and stores a portion of the first memory sector (4) in temporary memory,
- a second cache (7) which images the second memory sector (6) and stores it in temporary memory,
- wherein the second cache (7) has the same storage capacity as the second memory sector (6) and
- wherein the second memory sector (6) is a RAM, a ROM, an EPROM or an EEPROM.
Process for operation of a data processing device with the steps:
- Provision of a data processing device (1) which comprises a processor (2) and a memory (3),
- wherein the memory (3) has a first memory sector (4) and a second memory sector (6);
- imaging of the first memory sector (4) on a first cache (5);
- temporary storage of a portion of the first memory sector (4) in the first cache (5);
- imaging of the second memory sector (6) on a second cache (7),
- temporary storage of the second memory sector (6) in the second cache (7),
- wherein the second cache (7) has the same storage capacity as the second memory sector (6) and
- wherein no displacement cycles take place in the second cache (7);
- selecting a program code segment for storage in the second memory sector.
Dependencies are inferred from the claim text.