Segmented distributed memory module cache
AssigneeIntel Corporation
InventorHoward S. David
Life of this patent
Estimating the term…
Abstract
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. This embodiment includes an option to segment the cache. When the cache is segmented, the cache line size is halved. The segmentation allows the entire cache to be accessed without doubling the amount of tag address storage locations. The non-segmented cache may be used for memory systems using a burst length of eight bytes, while the segmented cache may be used for memory systems using a burst length of four bytes.
Claims15
An apparatus, comprising:
- an array of tag address storage locations;
- and
- a command sequencer and serializer unit coupled to the array of tag address storage locations, the command sequencer and serializer unit to control a data cache associated with a memory module, each tag address storage location in the array of tag address storage locations corresponding to a cache line divided into two segments.
An apparatus, comprising:
- a memory device;
- and
- a data cache coupled to the memory device, the data cache controlled by commands delivered by a memory controller component over a memory bus, the memory controller component including an array of tag address storage locations, each tag address storage location in the array of tag address storage locations corresponding to a cache line divided into two segments.
A system, comprising:
- a processor;
- a memory controller coupled to the processor, the memory controller including
- an array of tag address storage locations, and
- a command sequencer and serializer unit coupled to the array of tag address storage locations;
- and
- a memory module coupled to the memory controller, the memory module including
- a memory device, and
- a data cache coupled to the memory device, the data cache controlled by commands delivered by the memory controller, each tag address storage location in the array of tag address storage locations corresponding to a cache line divided into two segments.
Dependencies are inferred from the claim text.