Method and apparatus for implementing loop compression in a program counter trace

A system for storing program counter trace information, comprising:

• a content addressable memory that compares a new instruction address with instruction addresses stored in the content address memory, and which generates a store signal if the new instruction address does not match the instruction addresses stored in the content addressable memory;
• a memory device that receives the store signal and stores the new instruction address;
• and
• wherein the content addressable memory has a programmable depth, and wherein said content addressable memory receives a depth signal that indicates the programmed depth value for the content addressable memory.

A system for storing program counter trace information, comprising:

• a content addressable memory that compares a new instruction address with instruction addresses stored in the content address memory, and which generates a store signal if the new instruction address does not match the instruction addresses stored in the content addressable memory;
• a memory device that receives the store signal and stores the new instruction address;
• and
• wherein the content addressable memory has an associated mask that determines which bits of the new instruction address should be considered when comparing to the instruction addresses stored in the content addressable memory.