Distributed memory module cache prefetch
AssigneeIntel Corporation
InventorHoward S. David
Life of this patent
Estimating the term…
Abstract
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. One intended advantage of this example embodiment is the ability to read a current line of data out of a memory module DRAM and to load the next cache line of data into the memory module data cache. This allows the utilization of excess DRAM interconnect bandwidth while preserving limited memory bus bandwidth.
Claims27
An apparatus, comprising:
- an array of tag address storage locations;
- and
- a command sequencer and serializer unit coupled to the array of tag address storage locations, the command sequencer and serializer unit to control a data cache associated with a memory module, the command sequencer and serializer unit to cause a current line of data to be read out of a memory module memory device and to load a next line of data from the memory module memory device to the data cache.
An apparatus, comprising:
- at least one memory device;
- and
- a data cache coupled to the memory device, the data cache controlled by a plurality of commands delivered by a memory controller component over a memory bus, the memory controller component including an array of tag address storage locations, the plurality of commands including a read and preload command.
A system, comprising:
- a processor;
- a memory controller coupled to the processor, the memory controller including
- an array of tag address storage locations, and
- a command sequencer and serializer unit coupled to the array of tag address storage locations;
- and
- a memory module coupled to the memory controller, the memory module including
- at least one memory device, and
- a data cache coupled to the memory device, the data cache controlled by a plurality of commands delivered by the memory controller, one of the plurality of commands including a read and preload command.
A method, comprising:
- receiving a read and preload command at a memory module;
- reading a current line of data from at least one memory device;
- reading a next line of data from the memory device;
- and
- loading the next line of data into a data cache located on the memory module.
Dependencies are inferred from the claim text.