Method and system for accessing memory devices

A method of providing data to a set of pins of a device, the method comprising the steps of:

• during a first mode of operation, multiplexing a first set of data onto the set of pins to allow the set of pins to provide data representing two least significant bits of a first address, a most significant bit of the first address, and a lane enable;
• during a second mode of operation, multiplexing a second set of data onto the set of pins to allow the set of pins to provide data representing one least significant bit of a second address, a most significant bit of the second address, and two lane enables;
• and
• during a third mode of operation, multiplexing a third set of data onto the set of pins to allow the set of pins to provide four lane enables.

An apparatus comprising:

• a set of address nodes to provide address data for address location A(n) through A(2), where A(n) represents a most significant bit for at least a first mode of operation;
• a first output node to provide one of an address data for address location A(1) and a data lane enable signal based upon a mode of operation;
• a second output node to provide one of an address data for address location A(0) and a data lane enable signal based upon the mode of operation;
• and
• a third output node to provide one of an address data for address location A(n+1) and a data lane enable signal based upon the mode of operation.

An apparatus comprising:

• a first register having an output to indicate one of a first mode of operation and a second mode of operation;
• an address control portion having an input coupled to the output of the first register, and an output to indicate a value of an address bit when in the first mode of operation;
• a first data lane enable control portion having an input coupled to the output of the first register, and an output to indicate a first data lane enable value when in the second mode of operation;
• and
• an output pin coupled to the output of the address control portion and the output of the first data lane enable control portion.

A system comprising:

• a processing module coupled to a set of outputs;
• and
• memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to:
• utilize a first output to provide a first data lane enable to facilitate accessing of a portion of a first memory storage location associated with a first memory address when in a first mode of operation;
• and
• utilize the first output to provide an address bit of a second memory address to facilitate designation of a second memory storage location when in a second mode of operation.