Method and apparatus for eliminating the software generated ready-signal to hardware devices that are not part of the memory coherency domain

A method of notifying a hardware device in a computer system that information from a software stream executed by a microprocessor is available in a main memory array first-in/first-out (FIFO) buffer, the method comprising:

• allowing the hardware device to participate in a coherency domain of the computer system by the hardware device having a coherent cache memory duplicating a cache line of the FIFO buffer;
• writing information to the cache line of the FIFO buffer by the software stream;
• and
• notifying the hardware device that the information is available in the FIFO buffer by invalidating the duplicate copy of the cache line of the FIFO buffer in the onboard cache memory of the hardware device.

A method of transferring data between a software program executed on a microprocessor and a hardware device coupled to an expansion bus in a computer system, the method comprising:

• providing an exchange buffer in main memory;
• providing a duplicate copy of at least part of the exchange buffer in the hardware device;
• writing data by the software program into the exchange buffer, making the data in the exchange buffer different than the duplicate copy of the exchange buffer in the hardware device;
• invalidating the duplicate copy of the at least part of the exchange buffer in the hardware device;
• and
• reading the exchange buffer contents by the hardware device responsive to the invalidating step.

A computer system comprising:

• a microprocessor means for executing software programs, the microprocessor means having a cache means;
• a main memory means for providing program and data storage, a portion of the main memory means designated a buffer means for providing data exchange;
• a first bridge means for coupling the microprocessor means and the main memory means, the first bridge means also for implementing at least a portion of a cache coherency protocol to keep the cache means and the main memory means coherent;
• a second bridge means for providing protocol translation between a first communication bus means and a second communication bus means, the first communication bus means for coupling the first bridge means to the second bridge means;
• and
• a hardware device means for providing hardware specific tasks, the hardware device means coupled to the second bridge means by the second communication bus means, wherein the hardware device means has an cache memory means for duplicating a portion of the buffers means, and wherein the cache memory means is kept coherent by way of the cache coherency protocol.