Memory bus termination with memory unit having termination control
AssigneeIntel Corporation
InventorsJames M. Dodd, Narendra S. Khandekar
Life of this patent
Estimating the term…
Abstract
Methods and apparatus for a memory system using line termination circuits in each memory unit (e.g., integrated circuit memory device) are disclosed. The memory unit contains termination control logic that sets the state of a controllable termination circuit to control reflections on the data bus. The termination control logic determines the proper state for the termination circuit from the state of its memory unit, and in some cases, from the approximate state of the data bus as gleaned from commands decoded from the command/address bus. A termination configuration register on the unit can be used to define the appropriate termination state for each unit state and/or data bus state.
Claims30
A memory system comprising:
- an address/command bus;
- a multidrop data bus having a predetermined number of data signaling lines;
- a memory controller to transmit address and command signals on the address/command bus, and to transmit and receive data signals on the multidrop data bus corresponding to the address and command signals;
- and
- first and second memory units, each connected to both the address/command bus and the multidrop data bus, at least the second memory unit comprising controllable termination circuitry having on and off states and coupled to the multidrop data bus, and termination control logic to set the state of the termination circuitry according to decoded commands received on the address/command bus.
A memory device comprising:
- a memory cell array;
- a bi-directional data port capable of receiving data for and transmitting data stored in the memory cell array;
- an address and command port;
- a controllable line termination circuit to terminate signals at the data port, the circuit having on and off states;
- an address and command decoder to receive signals at the address and command port;
- and
- termination control logic coupled to the address and command decoder to set the state of the termination circuitry according to decoded commands from the decoder.
A memory controller comprising:
- an address/command generator to generate address and command signals for multiple memory units, including READ command signals, wherein the READ command signals identify the memory unit currently being addressed.
A method of operating a memory device comprising:
- terminating an external data bus on the memory device with a controllable line termination circuit having on and off states;
- monitoring the state of the memory device;
- and
- setting the state of the line termination circuit based on the state of the memory device.
A method of operating a memory system having a memory controller and at least two memory units, all connected to a command/address bus and a multidrop data bus, the method comprising:
- the memory controller indicating on the command/address bus, when issuing a read or write command to one of the memory units, which memory unit is the target of the command;
- each memory unit decoding the issued read or write command;
- and
- each memory unit setting the state of line termination circuitry, having on and off states, based on the decoded command.
An article of manufacture containing computer instructions that, when executed by a processor, perform a method comprising transferring a register value to a termination parameter register in a memory unit served by a data bus, the register value including fields to indicate, to the memory unit, state conditions under which the memory unit should enable and/or disable a data bus line termination circuit on the memory unit.
Dependencies are inferred from the claim text.