US 2003/0126334 A1 · Bus capability voting mechanism

Abstract

A computer system is disclosed having a bus capability determination mechanism. In a preferred embodiment, the computer system includes a backplane having sockets into which system and peripheral boards may be inserted. The sockets are coupled together by a backplane bus that includes a bus capability line. Each board preferably includes a voting circuit that, when enabled, limits the voltage on the capability signal line to no more than a predetermined voltage that is indicative of the capability of the board. The voltage on the capability signal line will thus be determined by the board having the lowest voltage limit. The clock source for the bus can then be set to the clock rate indicated by the voltage on the capability signal line. Zener devices are preferably used to carry out the voting operation, and may be disabled after the voting operation is complete.

Claims22

Dependent claims

A computer system comprising:

a backplane that includes:
multiple sockets;
a bus that couples the multiple sockets together,
wherein the bus includes a capability signal line;
and
a circuit board inserted in one of the multiple sockets, and configured to limit a voltage on the capability signal line to one of three or more predetermined values, wherein the predetermined values are indicative of different bus component capability levels.

3 more elements

Dependencies are inferred from the claim text.

Bus capability voting mechanism

Life of this patent

Bus capability voting mechanism

Life of this patent

Abstract

Claims22