Daisy chain latency reduction
AssigneeIntel Corporation
InventorsDavid S. Bormann, Kirk W. Skeba
Life of this patent
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Abstract
Transmitting data on a serial data transmission path includes reading at least one bit of a device address, wherein the device address is coupled with a serial data word and the serial data word is transmitted across a first link of a first serial data transmission path to a first device having an address. The serial data word is passed across a second link of the first serial data transmission path to a second device if the at least one bit of the device address does not match at least one corresponding address bit of the first device.
Claims40
A method comprising:
- reading at least one bit of a device address, wherein the device address is coupled with a serial data word and the serial data word is transmitted across a first link of a first serial data transmission path to a first device having an address;
- and
- passing the serial data word across a second link of the first serial data transmission path to a second device if the at least one bit of the device address does not match at least one corresponding address bit of the first device.
A computer readable medium containing executable computer program instructions, which when executed by a data processing system, cause the data processing system to perform a method comprising:
- reading at least one bit of a device address, wherein the device address is coupled with a serial data word and the serial data word is transmitted across a first link of a first serial data transmission path to a first device having an address;
- and
- passing the serial data word across a second link of the first serial data transmission path to a second device if the at least one bit of the device address does not match at least one corresponding address bit of the first device.
A computer readable medium containing executable computer program instructions, which when executed by a data processing system, cause the data processing system to perform a method comprising:
- transmitting a serial data word across a first link of a first serial data transmission path to a first device having an address, the serial data word having a device address comprised of at least one bit;
- reading the at least one bit of the device address by the first device;
- and
- passing the serial data word across a second link of the first serial data transmission path to a second device if the at least one bit of the device address does not match at least one corresponding address bit of the first device.
An apparatus comprising:
- a first device coupled with a first serial data transmission path, the first serial data transmission path having a first link and a second link, wherein the first device to read at least one bit of a device address coupled with a serial data word, to be transmitted across the first link of the first serial data transmission path and the first device to pass the serial data word across the second link of the first serial data transmission path to a second device if the at least one bit of the device address does not match at least one corresponding address bit of the first device.
An apparatus comprising:
- a first serial data transmission path having a first link and a second link;
- a controller to transmit a serial data word across the first serial data transmission path, the serial data word having a device address comprised of at least one bit;
- a first device having an address, wherein the first device is coupled with the first serial data transmission path;
- and
- a second device coupled with the first serial data transmission path, wherein the first device to read the at least one bit of the device address of the serial data word and if the at least one bit of the device address of the serial data word does not match a portion of the address of the first device then the first device to pass the serial data word across the second link of the first serial data transmission path to the second device.
Dependencies are inferred from the claim text.