Supercharge message exchanger
AssigneeEmulex Design & Manufacturing Corporation
InventorsMichael Liu, Bradley Roach, Sam Su, Peter Fiacco
Life of this patent
Estimating the term…
Abstract
A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.
Claims64
A system comprising:
- a first channel comprising a first direct memory access (DMA) engine, a second DMA engine, a first random access memory (RAM) and a first processor;
- and
- a second channel comprising a third DMA engine, a fourth DMA engine, a second RAM and a second processor.
A channel comprising:
- a random access memory (RAM) configured to store input/output completions;
- first and second engines configured to send input/output completions to the random access memory;
- and
- a processor configured to process the input/output completions stored in the random access memory.
A method comprising:
- configuring a random access memory (RAM) of a first channel to store input/output (I/O) completions from an engine in a second channel;
- and
- processing I/O completions in the RAM of the first channel.
A method comprising:
- detecting whether an engine of a first channel is inactive;
- if the engine of the first channel is inactive, storing input/output (I/O) completions from an engine in a second channel to a random access memory of the first channel;
- and
- processing the I/O completions in the random access memory of the first channel.
A method comprising:
- receiving input/output (I/O) completions from a plurality of data paths;
- storing the I/O completions in a plurality of registers, each register being configured to store an I/O completion from a predetermined data path;
- and
- transferring the I/O completions from the registers to a plurality of logical blocks of a random access memory, each logical block being configured to store I/O completions from a predetermined data path.
Dependencies are inferred from the claim text.