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AssigneeSTMicroelectronics S.r.l.
InventorStefano Surico
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An interface is provided for an integrated system that includes internal circuits, with each internal circuit functioning based upon its own clock. The interface includes a finite state machine for managing asynchronous and independent interactions between the internal circuits and external circuits. The finite state machine functions based upon a unique clock and a unique reset. The interface also includes an arbitration circuit connected to the finite state machine for receiving input signals for the finite state machine. The arbitration circuit includes a memory buffer for storing signals generated by the internal circuits when the finite state machine is performing an evaluation. The interface may be used to form a command interpreter of a non-volatile memory device.
An interface comprising a finite state machine and logic circuits for adapting it to a given specification, for managing asynchronous and independent interactions between external circuits, by way of user commands, and a plurality of internal circuits each functioning with a clock generally different from the clock of other internal circuits, of an integrated digital system, characterized in that said finite state machine is defined to work with a unique clock and unique reset and by the fact that said interface further comprises
A FLASH_EEPROM device comprising a command interpreter circuit for recognizing, according to a given specification, the operations required from the memory device through command codes and implementing a handshake with corresponding digital circuits that constitute the memory device, each functioning with its own clock, generally different from the one another, characterized in that said command interpreter circuit comprises a single clock and a single reset finite state machine and an arbitration structure of the clock signals of said digital circuits from which commands come from, providing to said finite state machine said single clock and said single reset signals.
A method of managing a finite state machine through an input arbitration structure having a memory buffer for storing a command to be executed by feeding codes and/or data to respective inputs of said finite state machine and a clock signal to a timing input of said finite state machine, comprising the following steps:
Dependencies are inferred from the claim text.