Back to results
US 2003/0126186 A1Published application
Method and apparatus for suspending execution of a thread until a specified memory access occurs
AssigneeIntel Corporation
InventorsDion Rodgers, Deborah T. Marr, David L. Hill, Shiv Kaushik, James B. Crossland, David A. Koufaty
Life of this patent
Estimating the term…
Abstract
Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.
Claims69
A processor comprising:
- a plurality of execution units to allow execution of a plurality of threads, including a first thread, said first thread having a first instruction having an associated address operand indicating a monitor address;
- suspend logic to suspend execution of said first thread;
- a monitor to cause resumption of the first thread in response to a memory access to the monitor address.
A processor comprising:
- a front end to receive a first instruction from a first thread and a second instruction from the first thread, the first instruction indicating a monitor address;
- execution resources to execute the first instruction and the second instruction and to suspend execution of said first thread in response to the second instruction;
- a monitor to cause resumption of the first thread in response to a memory access to the monitor address.
A processor comprising:
- front end logic to receive a first instruction from a first thread, the first instruction having an associated monitor address;
- a monitor coupled to receive the monitor address, and in response to said first instruction to monitor memory accesses to said monitor address and to signal an event when an access to said monitor address occurs.
A processor comprising:
- a plurality of execution units to execute a plurality of threads;
- front end logic to receive an instruction from a first thread of said plurality of threads;
- suspend logic to suspend said first thread in response to said instruction if no monitor events are pending, and to allow other ones of said plurality of threads to execute.
A processor comprising:
- a plurality of thread partitionable resources to receive instructions;
- a plurality of shared resources to execute instructions in cooperation with said plurality of thread partitionable resources;
- thread suspension logic to suspend a first thread in response to an instruction in said first thread, said thread suspension logic to relinquish partitions of said plurality of thread partitionable resources associated with the first thread in addition to suspending the first thread;
- a monitor to cause said processor to re-partition said plurality of thread partitionable resources and to resume execution of said first thread in response to an access to a memory address indicated by the first thread.
1 more element
An apparatus comprising:
- means for suspending a first thread of a plurality of threads of execution;
- means for detecting an access to a memory location;
- means for resuming said first thread in response to the means for detecting detecting the access to the memory location.
A method comprising:
- receiving a first opcode in a first thread of execution, said first opcode having an associated address operand which indicates a monitor address;
- suspending said first thread;
- detecting a memory access to the monitor address;
- resuming said first thread in response to detecting the memory access to the monitor address.
1 more element
A method comprising:
- receiving a first opcode executing in a first thread of execution;
- translating a linear address associated with said first opcode into a physical address;
- executing a bus transaction by a monitoring bus agent to ensure no other bus agent has sufficient ownership of data associated with said physical address to allow another bus agent to modify the data without informing the monitoring bus agent;
- monitoring for a write access to said physical address;
- signaling a hit if another bus agent reads said physical address;
- receiving a second opcode in the first thread of execution;
- suspending said first thread of execution and enabling recognition of a monitor event in response to the second opcode;
- resuming said first thread if the write access occurs;
- resuming execution of the first thread in response to any one of a first set of events;
- ignoring a second set of events.
7 more elements
A system comprising:
- a memory to store a first instruction from a first thread, the first instruction having an associated address operand indicating a monitor address;
- a first processor coupled to said memory, said first processor to enable a monitor to monitor memory transactions to detect a memory access to said monitor address in response to the first instruction and to cause resumption of said first thread in response to the memory access to the monitor address.
An article comprising a computer readable medium, which represents a processor comprising:
- a plurality of execution units to allow execution of a plurality of threads, including a first thread, said first thread having a first instruction having an associated address operand indicating a monitor address;
- suspend logic to suspend execution of said first thread;
- a monitor to cause resumption of the first thread in response to a memory access to the monitor address.
Dependencies are inferred from the claim text.