Symmetric cascaded domino carry generate circuit

An apparatus comprising:

• a first output to provide a precharge value during a precharge phase and a true carry generate value during an evaluation phase;
• a second output to provide the precharge value during the precharge phase and the compliment of the true carry generate true during the evaluation phase;
• a current input;
• a first evaluation block connected to the current input and the first output and having a plurality of transistors, wherein a number of said transistors are connected in a parallel relationship and a number of said transistors are connected in a serial relationship;
• and
• a second evaluation block connected to the current input and the second output and having a plurality of transistors, wherein the second evaluation block has the same number of transistors connected in a parallel relationship as the first evaluation block and the same number of transistors connected in a serial relationship as the first evaluation block.

An apparatus comprising:

• a true sum to provide a precharge signal during the precharge phase and the result of a sum function during the evaluation phase;
• a compliment sum output to provide the precharge signal during the precharge phase and the compliment of the true sum output during the evaluation phase;
• a first evaluation block connected to a current input, the true sum output, and the compliment sum output, wherein the first evaluation block has a plurality of transistors, and wherein a number of said transistors are connected in parallel and a number of said transistors are connected in serial;
• and
• a second evaluation block connected to the current input and the true sum output and having a plurality of transistors, wherein the second evaluation block has the same number of transistors connected in parallel as the first evaluation block and the same number of transistors connected in serial as the first evaluation block.

A method comprising:

• receiving at a first evaluation block three true input values;
• receiving at a second evaluation block three compliment input values, wherein the compliment input values are the compliment of the true input values;
• processing the true input values at the second evaluation block to provide a carry generate value at a first output by selecting one of a plurality of stacks of transistors in the second evaluation block, wherein each of said stacks of transistors connects a current input to a first output;
• and
• processing the compliment input values at the first evaluation block to provide the compliment of the carry generate value at a second output by selecting one of a plurality of stacks of transistors in the first evaluation block, wherein each of said stacks of transistors connects said current input to a second output, and wherein the first evaluation block and second evaluation block have the same number of stacks of transistors.