Circuitry for carrying out square root and division operations
AssigneeSTMicroelectronics S.r.l.
InventorTariq Kurd
Life of this patent
Estimating the term…
Abstract
The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry utilizes common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division operation is to be performed. The iteration circuitry is controlled in accordance with whether a square root or division operation is to be performed.
Claims20
Circuitry for carrying out a square root operation and a division operation, said circuitry comprising:
- common iteration circuitry for carrying out a plurality of iterations;
- and
- means for identifying if a square root operation or a division operation is to be performed, said iteration circuitry being controlled in accordance with whether a square root or division operation is to be performed.
Circuitry for performing a square root or division operation, said circuitry comprising:
- a plurality of sets of iteration circuitry, at least one of sets of iteration circuitry being connected to the output of the another of said sets of iteration circuitry, each of said sets of iteration circuitry comprising:
- a quotient selection logic part which is arranged to make a decision as to what is to be done to a remainder of a previous iteration in a current iteration,
- a determination part arranged to receive an output from the quotient selection logic part and based on the received output to determine a value to be added to said remainder of a previous iteration,
- a carry save adder part which adds the determined value to said remainder, and
- a remainder part is arranged to perform similar functions to the determination part and said carry save adder part.
Circuitry for carrying out an arithmetic operation requiring a plurality of iterations, said circuitry comprising:
- N sets of iteration circuitry arranged one after the other so that at least one of said sets of iteration circuitry is arranged to receive an output from a preceding one of said sets of iteration circuitry, each of said sets of iteration circuitry being arranged to carry out substantially the same operation, wherein at least one of said sets of iteration circuitry has different circuitry to that of at least one other of said sets of iteration circuitry.
Dependencies are inferred from the claim text.