Self-timed digital processing circuits

A OHRNS arithmetic processing module comprising:

• an OHRNS arithmetic processing transistor array having at least one multiple line data input and at least one multiple line data output;
• a delay circuit receiving a control signal at input and producing a delayed control signal at output, the delay circuit having an equal number of transistors in parallel with the input of the delay circuit as are in parallel with one of the lines of the multiple line data input of the OHRNS arithmetic processing transistor array, the delay circuit also having an equal number of transistors in parallel with the output of the delay circuit as are in parallel with one of the lines of the multiple line data output of the OHRNS arithmetic processing transistor array;
• and
• an output latch coupled to the OHRNS arithmetic processing transistor array and the delay circuit, the output latch latching the multiple line data output of the OHRNS arithmetic processing transistor array based on the delayed control signal produced by the delay circuit.

An asynchronous system comprising:

• a plurality of digital signal processing circuit modules, each of the digital signal processing circuit modules having at least one data input, at least one data output, a control input, and a control output;
• and
• a plurality of control units, each of the control units being coupled to the control output of one of the digital signal processing circuit modules,
• wherein at least one of the digital signal processing circuit modules includes:
• an isochronous data processing circuit coupled to the data input of the digital signal processing circuit module, the isochronous circuit having a uniform processing delay to determine the data output for all valid data inputs;
• a delay circuit coupled to the control input of the digital signal processing circuit module, the delay circuit producing a delayed control signal by delaying by a time period that is substantially equal to the uniform processing delay of the data processing circuit;
• and
• an output latch coupled to an output of the data processing circuit and to the delay circuit, the output latch latching the output of the data processing circuit based on the delayed control signal produced by the delay circuit.

A self-timed OHRNS processing circuit comprising:

• a first processing module producing a data output and an Ack output, the Ack output being toggled when the data output of the first processing module is ready;
• a second processing module coupled to the first processing module, the second processing module including a Req input, an Ack output, a transistor array, and a delay circuit, the Req input of the second processing module being coupled to the Ack output of the first processing module, the Ack output of the second processing module being toggled when the data output of the second processing module is ready, the transistor array having a uniform processing delay for producing the data output for all valid inputs, and the delay circuit delaying the Req input of the second processing module by a time period that is substantially equal to the uniform processing delay of the transistor array;
• a third processing module coupled to the second processing module, the third processing module including a Req input that is coupled to the Ack output of the second processing module;
• and
• a control unit coupled between the Ack output of the first processing module and the Req input of the second processing module, the control unit controlling the timing of the toggling of the Req input of the second processing module based at least partially on the Ack output of the first processing module.