Inter-queue ordering mechanism

A computer system implementing an inter-queue ordering mechanism between different queues of an interconnect, comprising:

• a central processing unit(s);
• core logic connected to the central processing unit(s), the core logic including:
• a first circular queue;
• a second circular queue, the first and the second circular queues having an ordering dependency between them, wherein entries in the second circular queue are not allowed to pass entries in the first circular queue;
• a first counter;
• and
• a second counter, the first and the second counters adapted to increment whenever an entry is enqueued to or dequeued from the first circular queue, respectively.

A method of implementing an inter-queue ordering mechanism between different queues of a computer system, the method comprising:

• enqueuing transaction entries in a first circular queue in the computer system;
• enqueuing additional transaction entries in a second circular queue in the computer system;
• ordering the dequeuing of transaction entries in the first and the second circular queues, the ordering comprising preventing the additional transaction entries in the second queue from passing the transaction entries in the first circular queue;
• and
• incrementing a first counter and a second counter whenever an entry is enqueued to or dequeued from the first circular queue, respectively.

A device for implementing an inter-queue transaction ordering mechanism of a computer system, comprising:

• first queue means for holding transaction entries;
• second queue means for holding other transaction entries;
• means for ordering transaction handling between the first and the second queue means such that entries in the second queue means are not allowed to pass entries in the first queue means;
• and
• means for incrementing whenever an entry is enqueued to or dequeued from the first circular queue.