LSI design verification apparatus, LSI design verification method, and LSI design verification program

An apparatus for design verification using logical simulation of a circuit description, a plurality of hierarchies from top to bottom in accordance with abstraction of circuit components, the apparatus comprising:

• a circuit description reading unit configured to read the circuit description;
• an analysis unit configured to analyze a signal connection topologies between the hierarchies of the circuit description from top to bottom;
• a property generation unit configured to generate a property description constituted by a signal topology connected to a target module from the property description of a module providing an input to the target module, the target module being implemented by the circuit component;
• a first test bench generation unit configured to generate a test vector and a first test bench description;
• and
• a second test bench generation unit configured to generate a second test bench description for comparing a simulation output and a specification output from the property description of the target module.

A computer implemented method for design verification using logical simulation of a circuit description having a plurality of hierarchies from top to bottom in accordance with abstraction of circuit components, the method comprising:

• reading the circuit description;
• analyzing signal connection topologies between the hierarchies of the circuit description from top to bottom;
• storing data of the signal connection topologies to a data storing device;
• reading properties of target modules implemented by the circuit components in the circuit description;
• extracting a property part having a signal communicating between the target modules;
• extracting an output operation property, defining output operation in an output side module, and an expecting operation property, defining an expecting operation of an input side module among the properties of the target module;
• and
• comparing the output operation properties with the expecting operation properties.

A computer implemented method for design verification using logical simulation of a circuit description having a plurality of hierarchies from top to bottom in accordance with abstraction of circuit components, the method comprising:

• reading the circuit description;
• analyzing signal connection topologies between the hierarchies of the circuit description from top to bottom;
• generating a property description constituted by a signal topology connected to a target module from the property description of a module providing an input to the target module, the target module being implemented by the circuit components;
• generating a test vector and a first test bench description;
• and
• generating a second test bench description comparing a simulation output and a specification outputs from the property description of the target module.

A computer program product for use with a design verification apparatus, wherein the apparatus uses logical simulation of a circuit description having a plurality of hierarchies from top to bottom in accordance with abstraction of circuit components, the computer program product comprising:

• instructions configured to read the circuit description;
• instructions configured to analyze signal connection topologies between the hierarchies of the circuit description from top to bottom;
• instructions configured to store data of the signal connection topologies to a data storing device;
• instructions configured to read properties of target modules implemented by the circuit components in the circuit description;
• instructions configured to extract a property part having a signal communicating between the target modules;
• instructions configured to extract an output operation property, defining output operation in an output side module, and an expecting operation property, defining an expecting operation of an input side module among the properties of the target module;
• and
• instructions configured to compare the output operation properties with the expecting operation properties.

A computer program product for use with a design verification apparatus, wherein the apparatus uses logical simulation of a circuit description having a plurality of hierarchies from top to bottom in accordance with abstraction of circuit components, the computer program product comprising:

• instructions configured to read the circuit description;
• instructions configured to analyze signal topology connection topologies between the hierarchies of the circuit description from top to bottom;
• instructions configured to generate a property description constituted by a signal connected to a target module from the property description of a module providing an input to the target module, the target module being implemented by the circuit component;
• instructions configured to generate a test vector and a first test bench description;
• and
• instructions configured to generate a second test bench description comparing a simulation output and a specification output from the property description of the target module.