VHDL technology library method for efficient customization of chip gate delays
AssigneeInternational Business Machines Corporation
InventorsMarvin J. Rich, Ashutosh Misra
Life of this patent
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Abstract
A method and system update a VHDL technology library (306) to incorporate correlated delay values by reading the VHDL technology library (306), inserting a tpd_super_rise_time generic declaration and a tpd_super_fall_time generic declaration for every VHDL gate model in the VHDL technology library (306), initializing other generic variables in every VHDL gate model in the VHDL technology library to an equation representing a correlation policy; and outputting an updated VHDL technology library. Then, the method and system bind correlated delay constants in a 3-dimensional variable data array structure to a VHDL technology library (306) using a VHDL package embedded with the correlation delay data.
Claims15
A method comprising:
- storing a tpd_super_rise_time generic declaration and a tpd_super_fall_time generic declaration for every VHDL gate model in a VHDL technology library;
- initializing other generic variables corresponding to every VHDL gate model in the VHDL technology library to an equation representing a correlation policy;
- and
- storing an updated VHDL technology library including
- the tpd_super_rise_time generic declaration and the tpd_super_fall_time generic declaration for every VHDL gate model, and
- the initialized other generic variables.
A method comprising:
- binding correlated delay constants in a 3-dimensional variable data array structure to a VHDL technology library.
A method comprising:
- using a tpd_super_rise_time generic declaration and a tpd_super_fall_time generic declaration, each generic declaration comprising at least one pointer, for every VHDL gate model in a VHDL technology library to index into a 3-dimensional variable data array structure comprising delay values;
- and
- resolving the pointers when VHDL modules are linked together.
A system comprising:
- a processor/controller;
- and
- a memory for storing a VHDL technology library and a VHDL technology library modifier, the memory communicatively coupled to the processor/controller, for
- inserting a tpd_super_rise_time generic declaration and a tpd_super_fall_time generic declaration for at least one VHDL gate model in the VHDL technology library,
- initializing other generic variables in every VHDL gate model in the VHDL technology library to an equation representing a correlation policy, and
- storing an updated VHDL technology library including the tpd_super_rise_time generic declaration and the tpd_super_fall_time generic declaration for the at least one VHDL gate model, and including the initialized other generic variables.
A computer readable medium, comprising instructions for:
- storing a tpd_super_rise_time generic declaration and a tpd_super_fall_time generic declaration for every VHDL gate model in a VHDL technology library;
- initializing other generic variables corresponding to every VHDL gate model in the VHDL technology library to an equation representing a correlation policy;
- and
- storing an updated VHDL technology library including
- the tpd_super_rise_time generic declaration and the tpd_super_fall_time generic declaration for every VHDL gate model, and
- the initialized other generic variables.
A computer readable medium comprising instructions for:
- binding correlated delay constants in a 3-dimensional variable data array structure to a VHDL technology library.
A computer readable medium comprising instructions for:
- using a tpd_super_rise_time generic declaration and a tpd_super_fall_time generic declaration, each generic declaration comprising at least one pointer, for every VHDL gate model in a VHDL technology library to index into a 3-dimensional variable data array structure comprising delay values;
- and
- resolving the pointers when VHDL modules are linked together.
Dependencies are inferred from the claim text.