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US 2003/0125917 A1Published application
Size reduction techniques for vital compliant VHDL simulation models
AssigneeInternational Business Machines Corporation
InventorsMarvin J. Rich, Ashutosh Misra
Life of this patent
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Abstract
A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file (310) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file (314) containing the super generics for every instance of every logic gate in the logic model.
Claims34
A method comprising:
- storing a rise time generic variable and a fall time generic variable, the rise time generic variable comprising at least one rise time delay value and the fall time generic variable comprising at least one fall time delay value;
- selecting a rise time delay value and a fall time delay value in a VHDL standard delay file that correspond to an instance of a logic gate in a logic model;
- building a rise-time super generic value and a fall-time super generic value for the selected rise time delay value and fall time delay value, the rise-time super generic value representing a rise time delay value stored in the rise time generic variable and the fall-time super generic value representing a fall time delay value stored in the fall time generic variable.
A method comprising:
- extracting correlation delays from a VHDL standard delay file analysis file;
- generating a VHDL associative array structure;
- and
- outputting a correlation VHDL file.
1 more element
An apparatus comprising:
- a controller/processor;
- a data memory for storing a VHDL standard delay file and a rise time generic variable and a fall time generic variable, the rise time generic variable comprising at least one rise time delay value and the fall time generic variable comprising at least one fall time delay value;
- a program memory storing an SDF reducer, the program memory communicatively coupled to controller/processor and the data memory, for selecting a rise time delay value and a fall time delay value in a VHDL standard delay file that correspond to an instance of a logic gate in a logic model, and for building a rise-time super generic value and a fall-time super generic value for the selected rise time delay value and fall time delay value, the rise-time super generic value representing a rise time delay value stored in the rise time generic variable and the fall-time super generic value representing a fall time delay value stored in the fall time generic variable.
A system comprising:
- a data memory for storing a VHDL standard delay file;
- a VHDL standard delay file analysis file;
- a program memory storing an SDF reducer, the program memory communicatively coupled to the VHDL standard delay file and the VHDL standard delay file analysis file, for selecting a rise time delay value and a fall time delay value in a VHDL standard delay file that correspond to an instance of a logic gate in a logic model, and for building a rise-time super generic value and a fall-time super generic value for the selected rise time delay value and fall time delay value, the rise-time super generic value representing a rise time delay value stored in the rise time generic variable and the fall-time super generic value representing a fall time delay value stored in the fall time generic variable;
- and
- a reduced standard delay file, communicatively coupled to the SDF reducer.
2 more elements
A computer readable medium comprising instructions for:
- storing a rise time generic variable and a fall time generic variable, the rise time generic variable comprising at least one rise time delay value and the fall time generic variable comprising at least one fall time delay value;
- selecting a rise time delay value and a fall time delay value in a VHDL standard delay file that correspond to an instance of a logic gate in a logic model;
- building a rise-time super generic value and a fall-time super generic value for the selected rise time delay value and fall time delay value, the rise-time super generic value representing a rise time delay value stored in the rise time generic variable and the fall-time super generic value representing a fall time delay value stored in the fall time generic variable.
A computer readable medium comprising instructions for:
- extracting correlation delays from a VHDL standard delay file analysis file;
- generating a VHDL associative array structure;
- and
- outputting a correlation VHDL file.
1 more element
Dependencies are inferred from the claim text.