FET/bipolar integrated logic circuits

An integrated inverter circuit comprising:

• a Bipolar input transistor having a base, an emitter and a collector;
• a Bipolar output transistor having a base, an emitter and a collector;
• first and second power lines;
• a constant current source;
• the emitters of the input and output transistors being coupled to the second power line;
• the base of the input transistor being connected to a digital input terminal;
• the base of the output transistor being connected to the collector of the input transistor;
• the collector of the output transistor being connected to a digital output terminal;
• the collector of the input transistor being coupled to the first power line through the constant current source;
• the collector of the input transistor being connected to the digital input terminal;
• and
• wherein no transistor other than said input and output transistors is coupled between said input and output terminals.

An integrated NAND/AND circuit comprising:

• first, second and third integrated sub circuits, the first, second and third integrated sub circuits having first and second power lines;
• the first integrated sub circuit comprising;
• a first FET input transistor having a first gate, a first source and a first drain;
• a second FET output transistor having a second gate, a second source and a second drain;
• a first constant current source;
• the first gate being connected to a digital input terminal iin1;
• the second gate being connected to the first drain;
• the second drain being connected to a digital output terminal iout1;
• the first drain being coupled to the first constant current source through the first power line;
• the first drain being connected to the digital input terminal iin1;
• the second integrated sub circuit comprising;
• a third FET input transistor having a third gate, a third source and a third drain;
• a fourth FET output transistor having a fourth gate, a fourth source and a fourth drain;
• a second constant current source;
• the third gate being connected to a digital input terminal iin2;
• the fourth gate being connected to the third drain;
• the fourth drain being connected to a digital output terminal iout2;
• the third drain being coupled to the second constant current source through the first power line;
• the third drain being connected to the digital input terminal iin2;
• the third integrated sub circuit comprising;
• a fifth FET input transistor having a fifth gate, a fifth source and a fifth drain;
• a sixth FET output transistor having a sixth gate, a sixth source and a sixth drain;
• a third constant current source;
• the first, second, third, fourth, fifth and sixth sources being coupled to the second power line;
• the fifth gate being connected to a digital output terminal iout1, 2;
• the sixth gate being connected to the fifth drain;
• the sixth drain being connected to a digital output terminal iout;
• the fifth drain being coupled to the third constant current source through the first power line;
• the fifth drain being connected to the digital output terminal iout1, 2;
• the digital output terminal iout1, 2 being connected to digital output terminal iout1;
• the digital output terminal iout1, 2 being connected to digital output terminal iout2,
• wherein no transistor other than said first input and second output transistors is coupled between said input terminal iin1 and output terminal iout1;
• wherein no transistor other than said third input and fourth output transistors is coupled between said input terminal iin2 and output terminal iout2;
• wherein no transistor other than said fifth input and sixth output transistors is coupled between said output terminal iout1, 2 and output terminal iout;
• wherein individual currents at terminals iin1, iin2, iout1 and iout2 are logically related to a current at terminal iout1, 2 in accordance with a NAND function;
• and
• wherein individual currents at terminals iin1, iin2, iout1 and iout2 are logically related to a current at terminal iout in accordance with an AND function.

An integrated NAND/AND circuit comprising:

• first, second and third integrated sub circuits, the first, second and third integrated sub circuits having first and second power lines;
• the first integrated sub circuit comprising;
• a first Bipolar input transistor having a first base, a first emitter and a first collector;
• a second Bipolar output transistor having a second base, a second emitter and a second collector;
• a first constant current source;
• the first base being connected to a digital input terminal iin1;
• the second base being connected to the first drain;
• the second collector being connected to a digital output terminal iout1;
• the first collector being coupled to the first constant current source through the first power line;
• the first collector being connected to the digital input terminal iin1;
• the second integrated sub circuit comprising;
• a third Bipolar input transistor having a third base, a third emitter and a third collector;
• a fourth Bipolar output transistor having a fourth base, a fourth emitter and a fourth collector;
• a second constant current source;
• the third base being connected to a digital input terminal iin2;
• the fourth base being connected to the third drain;
• the fourth collector being connected to a digital output terminal iout2;
• the third collector being coupled to the second constant current source through the first power line;
• the third collector being connected to the digital input terminal iin2;
• the third integrated sub circuit comprising;
• a fifth Bipolar input transistor having a fifth base, a fifth emitter and a fifth collector;
• a sixth Bipolar output transistor having a sixth base, a sixth emitter and a sixth collector;
• a third constant current source;
• the first, second, third, fourth, fifth and sixth emitters being coupled to the second power line;
• the fifth base being connected to a digital output terminal iout1, 2;
• the sixth base being connected to the fifth drain;
• the sixth collector being connected to a digital output terminal iout;
• the fifth collector being coupled to the third constant current source through the first power line;
• the fifth collector being connected to the digital output terminal iout1, 2;
• the digital output terminal iout1, 2 being connected to digital output terminal iout1,
• the digital output terminal iout1, 2 being connected to digital output terminal iout2,
• wherein no transistor other than said first input and second output transistors is coupled between said input terminal iin1 and output terminal iout1;
• wherein no transistor other than said third input and fourth output transistors is coupled between said input terminal iin2 and output terminal iout2;
• wherein no transistor other than said fifth input and sixth output transistors is coupled between said output terminal iout1, 2 and output terminal iout;
• wherein individual currents at terminals iin1, iin2, iout1 and iout2 are logically related to a current at terminal iout1, 2 in accordance with a NAND function;
• and
• wherein individual currents at terminals iin1, iin2, iout1 and iout2 are logically related to a current at terminal iout in accordance with an AND function.

An integrated differential circuit comprising:

• first and second integrated sub circuits, the first and second integrated sub circuits having first and second power lines;
• the first integrated sub circuit comprising;
• a first FET transistor having a first gate, a first source and a first drain;
• a second FET transistor having a second gate, a second source and a second drain;
• first and second constant current sources;
• the first and second sources being coupled to the first constant current source through the second power line;
• the first gate being connected to a first digital input terminal;
• the second gate being connected to the first drain;
• the second drain being connected to a first digital output terminal;
• the first drain being coupled to the second constant current source through the first power line;
• the first drain being connected to the first digital input terminal;
• the second integrated sub circuit comprising;
• a third FET transistor having a third gate, a third source and a third drain;
• a fourth FET transistor having a fourth gate, a fourth source and a fourth drain;
• a third constant current source;
• the third and fourth sources coupled to the first constant current source through the second power line;
• the third gate being connected to a second digital input terminal;
• the fourth gate being connected to the third drain;
• the fourth drain being connected to a second digital output terminal;
• the third drain being coupled to the third constant current source through the first power line;
• the third drain being connected to the second digital input terminal;
• wherein a fifth FET transistor comprises the second constant current source;
• wherein a sixth FET transistor comprises the third constant current source;
• wherein no transistor other than said first and second transistors is coupled between said first input terminal and said first output terminal;
• and
• wherein no transistor other than said third and fourth transistors is coupled between said second input terminal and said second output terminal.

An integrated differential circuit comprising:

• first and second integrated sub circuits, the first and second integrated sub circuits having first and second power lines;
• the first integrated sub circuit comprising;
• a first Bipolar transistor having a first base, a first emitter and a first collector;
• a second Bipolar transistor having a second base, a second emitter and a second collector;
• first and second constant current sources;
• the first and second emitters being coupled to the first constant current source through the second power line;
• the first base being connected to a first digital input terminal;
• the second base being connected to the first collector;
• the second collector being connected to a first digital output terminal;
• the first collector being coupled to the second constant current source through the first power line;
• the first collector being connected to the first digital input terminal;
• the second integrated sub circuit comprising;
• a third Bipolar transistor having a third base, a third emitter and a third collector;
• a fourth Bipolar transistor having a fourth base, a fourth emitter and a fourth collector;
• a third constant current source;
• the third and fourth emitters coupled to the first constant current source through the second power line;
• the third base being connected to a second digital input terminal;
• the fourth base being connected to the third collector;
• the fourth collector being connected to a second digital output terminal;
• the third collector being coupled to the third constant current source through the first power line;
• the third collector being connected to the second digital input terminal;
• wherein a fifth Bipolar transistor comprises the second constant current source;
• wherein a sixth Bipolar transistor comprises the third constant current source;
• wherein no transistor other than said first and second transistors is coupled between said first input terminal and said first output terminal;
• and
• wherein no transistor other than said third and fourth transistors is coupled between said second input terminal and said second output terminal.