Method and system for type demotion of expressions and variables by bitwise constant propagation
AssigneeIntel Corporation
InventorsWilliams Ludwell Harrison III, Cotton Seed
Life of this patent
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Abstract
A method and system for type demotion of expressions and variables by bitwise propagation is disclosed. In one embodiment, a method, comprises determining when an operation on a larger data type may be replaced by the operation on a smaller data type having a reduced precision, wherein the operation is contained in code associated with a language implementation system; and replacing the operation on the larger data type by the operation on the smaller data type.
Claims28
1). A method, comprising:
- determining when an operation on a larger data type may be replaced by the operation on a smaller data type having a reduced precision,
- wherein the operation is contained in code associated with a language implementation system;
- and
- replacing the operation on the larger data type by the operation on the smaller data type.
2). The method of claim 1, further comprising:
- determining when a first variable of the larger data type may be replaced by a second variable of a smaller data type having the reduced precision;
- and
- replacing the first variable of the larger data type by the second variable of the smaller data type.
3). The method of claim 2, wherein replacing the operation and replacing the first variable are used for automatic vectorization for signal and media processors that provide vector operations on small fixed-point data types.
4). The method of claim 3, wherein the processors are MMX equipped.
5). The method of claim 3, wherein the processors are SSE equipped.
6). The method of claim 3, further comprising performing algebraic simplification on the code.
7). The method of claim 6, wherein the language implementation system performs bitwise constant propagation by abstract interpretation on the code.
8). A computer-readable medium having stored thereon a plurality of instructions, said plurality of instructions when executed by a computer, cause said computer to perform:
- determining when an operation on a larger data type may be replaced by the operation on a smaller data type having a reduced precision,
- wherein the operation is contained in code associated with a language implementation system;
- and
- replacing the operation on the larger data type by the operation on the smaller data type.
9). The computer-readable medium of claim 8 having stored thereon additional instructions, said additional instructions when executed by a computer for optimizing, cause said computer to further perform:
- determining when a first variable of the larger data type may be replaced by a second variable of a smaller data type having the reduced precision;
- and
- replacing the first variable of the larger data type by the second variable of the smaller data type
10). The computer-readable medium of claim 9 wherein replacing the operation and replacing the first variable are used for automatic vectorization for signal and media processors that provide vector operations on small fixed-point data types.
11). The computer-readable medium of claim 10, wherein the processors are MMX equipped.
12). The computer-readable medium of claim 10, wherein the processors are SSE equipped.
13). The computer-readable medium of claim 10, having stored thereon additional instructions, said additional instructions when executed by a computer for optimizing, cause said computer to further perform performing algebraic simplification on the code.
14). The computer-readable medium of claim 13, wherein the language implementation system performs bitwise constant propagation by abstract interpretation on the code.
15). A system, comprising:
- a processor;
- memory connected to the processor storing instructions for type demotion of expressions and variables by bitwise constant propagation executed by the processor;
- storage connected to the processor that stores a software code having a plurality of separately compilable routines,
- wherein the processor executes the instructions on the code to determine when an operation on a larger data type may be replaced by the operation on a smaller data type having a reduced precision,
- wherein the operation is contained in code associated with a language implementation system;
- and
- replace the operation on the larger data type by the operation on the smaller data type.
16). The system of claim 15, wherein the processor further determines when a first variable of the larger data type may be replaced by a second variable of a smaller data type having the reduced precision;
- and
- replaces the first variable of the larger data type by the second variable of the smaller data type.
17). The system of claim 16, wherein the processor replaces the operation and replaces the first variable to provide vector operations on small fixed-point data types.
18). The system of claim 17, wherein the processor is MMX equipped.
19). The system of claim 17, wherein the processor is SSE equipped.
20). The system of claim 18, wherein the processor performs algebraic simplification on the code.
21). The system of claim 19, wherein the language implementation system performs bitwise constant propagation by abstract interpretation on the code.
22). A system, comprising:
- means for determining when an operation on a larger data type may be replaced by the operation on a smaller data type having a reduced precision, wherein the operation is contained in code associated with a language implementation system;
- and
- means for replacing the operation on the larger data type by the operation on the smaller data type.
23). The system of claim 22, further comprising:
- means for determining when a first variable of the larger data type may be replaced by a second variable of a smaller data type having the reduced precision;
- and
- means for replacing the first variable of the larger data type by the second variable of the smaller data type.
24). The system of claim 23, wherein the means for replacing the operation and the means for replacing the first variable are used for automatic vectorization for signal and media processors that provide vector operations on small fixed-point data types.
25). The system of claim 24, wherein the processors are MMX equipped.
26). The system of claim 24, wherein the processors are SSE equipped.
27). The system of claim 24, further comprising means for performing algebraic simplification on the code.
28). The system of claim 27, wherein the language implementation system performs bitwise constant propagation by abstract interpretation on the code.