Method and its apparatus for manufacturing simiconductor device

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a thin film on an exposure substrate;
• applying resist on the exposure substrate;
• exposing a circuit pattern on an exposure original plate on said exposure substrate having said resist applied thereon;
• developing the exposed resist to form a pattern of the resist;
• and
• etching said substrate with use of the developed resist pattern as a mask to form a pattern of said thin film,
• wherein said exposure step further includes:
• a first step of linking the sectional shape of said resist pattern or a signal waveform associated with said sectional shape to deviations from the optimum values of the exposure light quantity and focus, and storing it as linked information;
• a second step of measuring a sectional shape of said product circuit pattern formed on said exposure substrate through said exposure step or a signal waveform associated with said sectional shape;
• a third step of calculating deviations from the optimum values of the exposure light quantity and focus of said product circuit pattern in said exposure step on the basis of said sectional shape of said product circuit pattern or said signal waveform associated with said sectional shape measured in said second step and on the basis of said linked information in said first step;
• and
• a fourth step of feeding said deviations from the optimum values of the exposure light quantity and focus of said product circuit pattern calculated in said third step back to said exposure step.

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a thin film on an exposure substrate;
• applying resist on said exposure substrate;
• exposing a circuit pattern on an exposure original plate onto the substrate having said resist applied thereon;
• developing the exposed resist to form a pattern of the resist;
• and
• etching said substrate with use of the pattern of the developed resist as a mask to form a pattern of said thin film,
• wherein said exposure step further includes:
• a first step of storing data for linking sectional shape information about a product circuit pattern to sectional shape information about a test pattern;
• a second step of measuring the test pattern;
• a third step of deviations from the optimum values of exposure conditions of said product circuit pattern in said exposure step on the basis of the shape information on said test pattern measured in said second step and the data stored in said first step;
• and
• a fourth step of feeding said deviations from the optimum values of the exposure conditions of said product circuit pattern calculated in said third step back to said exposure step.

A semiconductor device manufacturing system comprising:

• an exposure apparatus for exposing a product circuit pattern of an exposure original plate on the substrate;
• a scatterometry apparatus having a light source for irradiating light on a subject to be examined and a sensor for detecting light passed through said subject as a signal waveform, for measuring said signal waveform according to the surface shape of said subject;
• a history memory unit for storing a history of said exposure apparatus used in manufacturing of said substrate, illumination conditions and said exposure original plate;
• an original plate data memory unit for storing dimensions of the product circuit pattern of said exposure original plate, dimensions of the test pattern, coordinates of said product circuit pattern and coordinates of said test pattern;
• an illumination conditions memory unit for storing illumination conditions for said each exposure apparatus and each step;
• a wave aberration data memory unit for storing wave aberration data for said each exposure apparatus and each pattern coordinate;
• a pattern optimum value deviation calculation unit for calculating deviations from optimum values of the exposure light quantity and focus of said test pattern and said product circuit pattern from said illumination conditions, said dimensions of said product circuit pattern and test pattern, and the wave aberration for said each coordinate;
• a pattern optimum value deviation memory unit for storing said optimum value deviations;
• an FEM-linked library signal waveform memory unit for storing deviations from the optimum values of the exposure light quantity and focus and a signal waveform associated with the sectional shape of said test pattern as linked to said deviations;
• a waveform matching unit for calculating deviations from the optimum values of the exposure light quantity and focus of said test pattern by extracting most matched one of said signal waveforms stored in said FEM-linked library signal waveform memory unit with respect to said test pattern signal waveform of said substrate actually measured by said scatterometry apparatus;
• a correction calculation unit for calculating a correction of the exposure apparatus to said product circuit pattern from said deviations from the optimum values of the exposure light quantity and focus of said test pattern calculated by said waveform matching unit and from said optimum value deviations of said test pattern and said product circuit pattern stored in said pattern optimum value deviation memory unit;
• and
• a control unit for controlling said each unit, said scatterometry apparatus and data input/output between said exposure apparatuses.