Multidirectional router
AssigneeLSI Logic Corporation
InventorsAlexandre E. Andreev, Elyar E. Gasanov, Ranko Scepanovic
Life of this patent
Estimating the term…
Abstract
The present invention is directed to a system and method for providing multidirectional routing. The present invention may provide an arbitrary number of routing layers and an arbitrary direction on each of those layers to provide a smaller die size and to reduce power consumption by providing more flexibility for net routing directions.
Claims40
A method for routing a multi-layered integrated circuit, comprising:
- receiving parameters for an integrated circuit having n layers, wherein n is at least two;
- constructing a routing graph for a level k of the n layers of the integrated circuit, the k level partitioned into k-level tiles, wherein at least one edge is provided to join a first tile and a second tile in the k level routing graph;
- calculating capacities of the at least one edge joining the first tile and the second tile, the edge at least one of regular and normal;
- adding occupancies based on previous level net routing (k+1) and calculating penalties of edges;
- and
- routing nets based on the routing graph, calculated capacities and added occupancies.
A method for routing a multi-layered integrated circuit wherein arbitrary routing directions are supported on an arbitrary number of layers of the integrated circuit, comprising:
- receiving parameters for an integrated circuit having n layers, wherein n is at least two;
- constructing a routing graph for layers of the integrated circuit, the levels partitioned into tiles, wherein at least one edge is provided to join a first tile and a second tile in the routing graph, the tiles positioned generally corresponding to a layer grid line of the level;
- and
- routing based on the routing graph.
A system for routing a multi-layered integrated circuit, comprising:
- a memory suitable for storing a program of instructions;
- and
- a processor communicatively coupled to the memory, wherein the program of instructions configures the processor to receive parameters for an integrated circuit having n layers, wherein n is at least two;
- construct a routing graph for layers of the integrated circuit, the levels partitioned into tiles, wherein at least one edge is provided to join a first tile and a second tile in the routing graph, the tiles positioned generally corresponding to a layer grid line of the level;
- and
- route based on the routing graph.
A system for routing a multi-layered integrated circuit, comprising:
- a means for receiving parameters for an integrated circuit having n layers, wherein n is at least two;
- a means for constructing a routing graph for layers of the integrated circuit, the levels partitioned into tiles, wherein at least one edge is provided to join a first tile and a second tile in the routing graph, the tiles positioned generally corresponding to a layer grid line of the level;
- and
- a means for routing based on the routing graph.
Dependencies are inferred from the claim text.