Design method for integrated circuit chips
AssigneeNEC Electronics Corporation
InventorJunichi Goto
Life of this patent
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Abstract
A method of placing integrated circuit chips on a wafer uses a library of average delay time values of logic gates. Exposure-dependent delay time values of the logic gates, which result from exposure of a unit area to a beam of radiation, are additionally stored in the library. These delay time values are detected by successively exposing unit areas of a test wafer to a beam of radiation as a function of relative positions of each integrated circuit chip within the unit exposure area. In a modified embodiment, only one integrated circuit chip within each unit area is exposed to the radiation beam, and the exposure-dependent delay time values are detected as a function of position within the exposed integrated circuit chip or as a function of distance from the center of the each unit area.
Claims14
A computer-assisted design method of placing a plurality of integrated circuit chips on a semiconductor wafer by using a library in which average delay time values of logic gates are stored, comprising the steps of:
- a) storing a plurality of exposure-dependent delay time values of logic gates in said library, said exposure-dependent delay time values representing delay times resulting from exposure of each of a plurality of unit areas of said wafer to a beam of radiation;
- and
- b) calculating a propagation delay time based on the delay time values of said library.
A method of creating a library of delay time values for computer-assisted design of integrated circuit chips, comprising the steps of:
- detecting a plurality of device parameters from a plurality of groups of test chips, the test chips of each of the groups being formed on an identical position of a plurality of test wafers;
- calculating an average value of said device parameters detected from each of said groups of test chips to produce a plurality of chip-position dependent delay time values for a plurality of logic gates;
- and
- calculating a plurality of differences between said device parameters and said average value to produce a plurality of delay time values of random component for said logic gates;
- successively exposing a plurality of unit areas of a test wafer to a beam of radiation, each of said unit areas containing at least one test chip;
- detecting a plurality of device parameters from the test chips of said exposed unit areas to produce a plurality of exposure-dependent delay time values for said logic gates;
- and
- storing said chip-position dependent delay time values, said delay time values of random component, and said exposure-dependent delay time values in said library.
Dependencies are inferred from the claim text.