Method for generating register transfer level code
AssigneeHynix Semiconductor Inc.
InventorJong-Hong Bae
Life of this patent
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Abstract
A method for generating a register transfer level code, comprising the steps of: generating the generalized register transfer level code without considering process conditions; separating all logic gates into either a combinational logic circuit or a sequential logic circuit; transforming the register transfer level code of the separated combinational logic circuits and sequential logic circuits into each equivalent register transfer level code; and simplifying the combinational logic circuits and the sequential logic circuits into one simple code.
Claims8
A method for generating a register transfer level code, comprising steps of:
- a) generating the generalized register transfer level code without considering process conditions;
- b) separating all logic gates into either a combinational logic circuit or a sequential logic circuit;
- c) transforming the register transfer level code of the separated combinational logic circuits and sequential logic circuits into each equivalent register transfer level code;
- and
- d) simplifying the combinational logic circuits and the sequential logic circuits into one simple code.
A method for generating the register transfer level code including a three-state buffer, comprising steps of:
- a) generating a generalized register transfer level code without considering process conditions;
- b) separating all logic gates into either the combinational logic circuit or the sequential logic circuit and including the three-state buffer into the sequential logic circuit;
- c) transforming the register transfer level code of the separated combinational logic circuits and sequential logic circuits into each equivalent register transfer level code;
- d) simplifying the combinational logic circuits and the sequential logic circuits into one simple code.
A storage media for executing a method for generating a register transfer level code, comprising instructions performing steps of:
- a) generalizing each register transfer level code of a combinational logic circuit and a sequential logic circuit;
- b) separating the register transfer level codes of the generalized combinational logic circuit and the sequential logic circuit;
- c) transforming the register transfer level code of the separated combinational logic circuits and sequential logic circuits into each equivalent register transfer level code;
- and
- d) simplifying the combinational logic circuits and the sequential logic circuits into one simple code.
A storage media for executing a method for generating a register transfer level code in a logic circuit having a three-state buffer, comprising instructions performing steps of:
- a) generating the generalized register transfer level code without considering process conditions;
- b) separating all logic gates into either a combinational logic circuit or a sequential logic circuit;
- c) transforming the register transfer level code of the separated combinational logic circuits and sequential logic circuits into each equivalent register transfer level code;
- and
- d) simplifying the combinational logic circuits and the sequential logic circuits into one simple code.
Dependencies are inferred from the claim text.