Convolutional encoding using a modified multiplier

A broadband wireless communications device, comprising:

• an antenna;
• a radio subsystem, coupled to the antenna, for amplifying signals to be transmitted from the antenna;
• encode and modulate logic, coupled to the radio subsystem, for encoding digital signals to be transmitted, comprising:
• convolution coding logic, for applying a convolution code to at least one datastream corresponding to a subchannel in a broadband spectrum, and comprising:
• a sequence of delay stages, for storing successive states of a datastream;
• a plurality of code registers, each for storing a plurality of bits having states corresponding to a set of code generator polynomial coefficients;
• a code multiplexer for selecting one of the plurality of code registers;
• a parallel multiplier, comprising a plurality of adder units arranged in rows, each row associated with one of the plurality of bits of the selected code register, and each adder unit comprising:
• a first logic gate for gating the application of a corresponding one of the successive states of the datastream responsive to a corresponding bit of the first code register;
• and
• an adder for adding a sum bit from an adder unit in a previous row with the output of the first logic gate, selected ones of the outputs of the adder units in a last row of the parallel multiplier providing an encoded output of the coding circuit;
• and
• a spread and modulate function, for spreading the encoded datastream into a modulated broadband signal to be forwarded to the radio subsystem.

A broadband wireless communications device, comprising:

• an antenna;
• a radio subsystem, coupled to the antenna, for amplifying signals to be transmitted from the antenna;
• encode and modulate logic, coupled to the radio subsystem, for encoding digital signals to be transmitted, comprising:
• convolution coding logic, for applying a convolution code to at least one datastream corresponding to a subchannel in a broadband spectrum;
• and
• a spread and modulate function, for spreading the encoded datastream into a modulated broadband signal to be forwarded to the radio subsystem, comprising:
• a long code and spreading logic function;
• a scrambling code generator, for generating a scrambling code having in-phase and quadrature components, comprising:
• first and second sequences of delay stages, for storing successive states of first and second codestreams;
• a first code register, for storing a plurality of bits having states corresponding to a first feed-forward combination associated with the first sequence of delay stages;
• a second code register, for storing a plurality of bits having states corresponding to a second feed-forward combination associated with the second sequence of delay stages;
• a code register multiplexer, for selecting one of the code registers for application to the parallel multiplier;
• a parallel multiplier, comprising a plurality of adder units arranged in rows, each row associated with one of the plurality of bits of the first code register, and each adder unit comprising:
• a first logic gate for gating the application of a corresponding one of the successive states of the datastream responsive to a corresponding bit of the first code register;
• and
• an adder for adding a sum bit from an adder unit in a previous row with the output of the first logic gate, selected ones of the outputs of the adder units in a last row of the parallel multiplier provide an encoded output of the coding circuit;
• an output demultiplexer, for coupling a selected output of one of the adder units in a last row of the parallel multiplier to a selected node;
• an in-phase exclusive-OR function, having inputs coupled to a last one of the delay stages of each of the first and second sequences, for generating an in-phase scrambling code component value;
• a quadrature exclusive-OR function, having inputs coupled to respective outputs of the output demultiplexer, for generating a quadrature scrambling code component value;
• and
• feedback logic, coupled to the first and second sequences of delay stages, for generating and applying a feedback value to a first one of the delay stages of each of the first and second sequences of delay stages;
• and
• bit modulator circuitry, for modulating each of the in-phase and quadrature components of the encoded datastream with the in-phase and quadrature components, respectively, of the scrambling code.