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US 2003/0120993 A1Published application
Viterbi decoder using restructured trellis
AssigneeTexas Instruments Incorporated
InventorDarrell K. Cox
Life of this patent
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Abstract
Viterbi decoding is implemented using an asymmetrical trellis 70 having an A-trellis 72 and a B-trellis 74. The trellis 70 is designed for efficient implementation on a processing device 40 with arithmetic units 42 having multi-field arithmetic and logic capabilities By concurrently processing multiple path metrics in separate fields, a highly efficient decoder may be implemented in a software-controlled device.
Claims24
A method of performing Viterbi decoding function comprising the steps of:
- calculating candidate path metrics for states at time Tn based on previously calculated path metrics for states at time Tn−1 and branch metrics associated with transitions between said states at time Tn−1 and states at time Tn according to a first trellis;
- selecting path metrics for states at time Tn from said candidate path metrics;
- calculating candidate path metrics for states at Tn+1 based on said selected path metrics for states at Tn according to a second trellis, different from said first trellis.
A Viterbi decoder comprising:
- programmable processing circuitry for:
- calculating candidate path metrics for states at time Tn based on previously calculated path metrics for states at time Tn−1 and branch metrics associated with transitions between said states at time Tn−1 and states at time Tn according to a first trellis;
- selecting path metrics for states at time Tn from said candidate path metrics;
- calculating candidate path metrics for states at Tn+1 based on said selected path metrics for states at Tn according to a second trellis, different from said first trellis.
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Dependencies are inferred from the claim text.