Method and circuit to implement double data rate testing
OwnerJohn F. Zumkehrinventor
Life of this patent
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Abstract
A DDR apparatus is provided that includes a pattern generating device to generate a clock test pattern and a data test pattern and buffer devices to receive the clock test pattern and the data test pattern. A pattern checking device checks patterns received from the buffer devices. Clock generating logic controls a clock for the clock test pattern and a clock for the data test pattern.
Claims28
A DDR apparatus comprising:
- a pattern generating device to generate a clock test pattern and a data test pattern;
- and
- buffer devices to receive said clock test pattern and said data test pattern;
- a pattern checking device to check patterns received from said buffer devices;
- and
- clock generating logic to control a clock for said clock test pattern and a clock for said data test pattern.
A circuit comprising:
- a pattern generating device to generate a clock test pattern and a data test pattern for at least one DDR I/O cell;
- a pattern checking device to check patterns passing through said at least one DDR I/O cell;
- and
- clock generating logic to control a clock for said clock test pattern and a clock for said data test pattern.
A clock generating circuit to generate a first clock signal and a second clock signal for a DDR device, wherein said clock generating circuit generates said first clock signal in phase with said second clock signal when in a test mode and generates said first clock signal out of phase with said second clock signal when in a normal mode.
The clock generating circuit of claim 23, wherein said clock generation logic further includes state logic to control signals applied to said switching element.
A method comprising:
- generating a clock test pattern and a data test pattern;
- passing said clock test pattern and said data test pattern through at least one DDR device;
- checking patterns passing through said at least one DDR device;
- and
- adjusting one of a clock for said clock test pattern and a clock for said data test pattern.
Dependencies are inferred from the claim text.