Interconnections for plural and hierarchical P1500 test wrappers
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
This disclosure describes a test architecture for accessing IP core test wrappers within an IC and for accessing the wrappers using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper basically resides at the boundary of the core and provides a way to test the core and the interconnections between cores. While IEEE P1500 is standardizing the wrapper, it leaves the architectural arrangement of multiple and hierarchical wrappers within an IC up to the users of the P1500 standard.
Claims9
A test architecture within an integrated circuit comprising;
- A. a plurality of core wrappers each free of 1149.1 test access ports and each having a serial input, a serial output, and control inputs,
- B. input circuitry having a serial input, a plurality of serial outputs, and control inputs,
- C. output circuitry having a plurality of serial inputs, a serial output, and control inputs,
- D. first connections formed between ones of said plurality of serial outputs and ones of said serial inputs of said plurality of core wrappers, and
- E. second connections formed between ones of said serial outputs of said plurality of core wrappers and ones of said plurality of serial inputs.
Test circuitry within an integrated circuit comprising;
- A. a plurality of core wrappers each free of 1149.1 test access ports and each having a serial input, a serial output, and control inputs,
- B. output circuitry having inputs connected to the serial outputs of said core wrappers and having an output, and
- C. a shift register having an input connected to the output of said output circuitry.
A process of communicating serial data through first and second core wrapper arrangements within an integrated circuit comprising:
- A. performing a first serial data communication through a first core wrapper arrangement and a shift register external of said first core wrapper arrangement, and
- B. performing a second serial data communication through a second core wrapper arrangement and a shift register external of said second core wrapper arrangement.
A process of enabling access to a lower test architecture embedded within a higher test architecture comprising:
- A. performing a first scan operation to load a first code into a register of said higher test architecture;
- and
- B. performing a second scan operation to reload said first code into the register of said higher test architecture and to load a second code into a register of said lower test architecture.
An electronic system comprising;
- A. a plurality of circuits each having an input and an output,
- B. a data path formed between the output of a first of said plurality of circuits and the input of a second of said plurality of circuits, and
- C. circuitry within the data path selectively operating in one of a first mode to register the data from said output to said input and a second mode to directly pass the data from said serial output to said serial input.
Dependencies are inferred from the claim text.