Programable multi-port memory bist with compact microcode

A digital system, comprising:

• a device having a plurality of ports;
• a digital processor coupled to the device;
• and
• an apparatus for testing the device, said apparatus comprising:
• a plurality of subcontrollers, said plurality of subcontrollers coupled to the device, each subcontroller being adapted to execute a subinstruction of a plurality of subinstructions, each subinstruction directing a performance of at least one operation at one port of the plurality of ports;
• and
• a primary controller coupled to the plurality of subcontrollers, the primary controller being adapted to dispatch the plurality of subinstructions to the plurality of subcontrollers.

A method for testing a device having a plurality of ports, comprising the steps of:

• providing a plurality of subcontrollers;
• coupling a primary controller to the plurality of subcontrollers;
• coupling the plurality of subcontrollers to the plurality of ports of the device;
• dispatching by the primary controller a plurality of subinstructions to the plurality of subcontrollers;
• and
• executing by the plurality of subcontrollers the plurality of subinstructions, each subinstruction directing a performance of at least one operation at one port of the plurality of ports.

A method for testing a device coupled to a digital processor, comprising the steps of:

• providing the device coupled to the digital processor, said device having a plurality of ports;
• coupling a plurality of subcontrollers to the device;
• coupling a primary controller to the plurality of ports of the device;
• dispatching by the primary controller a plurality of subinstructions to the plurality of subcontrollers;
• and
• executing by the plurality of subcontrollers the plurality of subinstructions, each subinstruction directing a performance of at least one operation at one port of the plurality of ports.