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US 2003/0120965 A1Published application
Self-timed voltage-subtraction sneak current cancellation method and apparatus
AssigneeIntel Corporation
InventorHans Ola Dahl
Life of this patent
Estimating the term…
Abstract
A single bit line reference signal path or line is used for both voltage subtraction and self-timing of a second sense that is longer than a first sense in a dual-sense, single-read memory cell. The self-timing mechanism includes an analog circuit.
Claims26
A sensing method comprising:
- using a reference bit line to difference a charge on a memory cell as between a first and a second sense, and
- using the reference bit line also to self-time the second sense.
An apparatus comprising:
- a signal path representing a sneak charge of a memory cell bit;
- a subtractor coupled with said signal path to determine a difference between a first sneak charge during a first sense and a second sneak charge during a second sense;
- and
- a circuit to automatically adjust the second sense to be longer than the first sense in inverse proportion to the determined difference between the first sneak charge and the second sneak charge.
1 more element
A circuit comprising:
- a threshold generator to produce a reference signal;
- a self-time operational amplifier operatively coupled to said threshold generator to produce differential output signals representative of a difference between the reference signal and a bit line signal;
- a pair of capacitors having first terminals connected in series to said differential output signals;
- and
- a first comparator to compare signals present at second terminals of the pair of capacitors to produce a read timing signal for the memory cell.
2 more elements
A system comprising:
- a hard disk memory;
- and
- a cache memory coupled to the hard disk memory, wherein the cache memory comprises:
- a signal path representing a sneak charge of a memory cell bit;
- a subtractor coupled with the signal path to determine a difference between a first sneak charge during a first sense and a second sneak charge during a second sense;
- and
- a circuit to automatically adjust the second sense to be longer than the first sense in inverse proportion to the difference between the first sneak charge and the second sneak charge.
4 more elements
A system comprising:
- a hard disk memory;
- and
- a cache memory coupled to the hard disk memory, wherein the cache memory comprises:
- a threshold generator to produce a reference signal;
- an operational amplifier operatively coupled to said threshold generator to produce differential output signals representative of a difference between the reference signal and a bit line signal;
- a pair of capacitors having first terminals connected in series to said differential output signals;
- and
- a first comparator to compare signals present at second terminals of the pair of capacitors to produce a read timing signal for the memory cell.
5 more elements
Dependencies are inferred from the claim text.