Method and apparatus for enabling a low power mode for a processor
AssigneeIntel Corporation
InventorsXia Dai, John W. Horigan, Millind Mittal, Leslie E. Cline
Life of this patent
Estimating the term…
Abstract
In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicate the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.
Claims25
A processor comprising:
- a voltage supply input port to receive a voltage at a first voltage level;
- and
- a cache to flush or maintain, depending on a power status signal, its contents upon entering a low power state in which the voltage is to be received at a second voltage level, the second voltage level being lower than the first voltage level.
A computer system comprising:
- a voltage regulator to supply a voltage at a first voltage level and to supply the voltage at a lower second voltage level while in a low power state;
- a cache, to be powered by the voltage from the voltage regulator;
- and
- a power manager to send a first or second signal if power reduction associated with maintaining contents of the cache upon entering the low power state is a lower or higher priority, respectively, than avoiding an increase in a soft error rate in the cache associated with the low power state.
A computer system comprising:
- a voltage regulator to supply a voltage;
- a clock to provide a clock signal;
- and
- a processor to receive the clock signal and the voltage, the processor including a cache, the processor to flush or maintain, depending on a power status signal, contents of the cache upon entering a low power state in which the clock is off and the voltage is reduced.
A method comprising:
- triggering a processor of a computer system to enter a low power state in which a voltage supplied to a cache of the processor is reduced and a clock supplied to the processor is off;
- and
- flushing or maintaining contents of the cache upon entering the low power state depending on a power status signal.
Dependencies are inferred from the claim text.