Power management using processor throttling emulation
AssigneeIntel Corporation
InventorBarnes Cooper
Life of this patent
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Abstract
In one embodiment of the invention, a processor state of a processor is determined upon expiration of a system management interrupt (SMI) timer. The processor state is one of an operational state and a low power state. The SMI timer is loaded with a timer value based on the processor state. The timer value is one of a first value and a second value. The processor is transitioned to one of the operational state and the low power state according to the processor state.
Claims30
A method comprising:
- determining a processor state of a processor upon expiration of a system management interrupt (SMI) timer, the processor state being one of an operational state and a low power state;
- loading the SMI timer with a timer value based on the processor state, the timer value being one of a first value and a second value;
- and
- transitioning the processor to one of the operational state and the low power state according to the processor state.
A computer program product comprises:
- a machine useable medium having computer program code embedded therein, the computer program product having:
- computer readable program code to determine a processor state of a processor upon expiration of a system management interrupt (SMI) timer, the processor state being one of an operational state and a low power state;
- computer readable program code to load the SMI timer with a timer value based on the processor state, the timer value being one of a first value and a second value;
- and
- computer readable program code to transition the processor to one of the operational state and the low power state according to the processor state.
A system comprising:
- a processor;
- a memory coupled to the processor to store a throttling emulator, the throttling emulator, when executed, causing the processor to:
- determine a processor state of the processor upon expiration of a system management interrupt (SMI) timer, the processor state being one of an operational state and a low power state;
- load the SMI timer with a timer value based on the processor state, the timer value being one of a first value and a second value;
- and
- transition the processor to one of the operational state and the low power state according to the processor state.
The system of claim 31 wherein the throttling emulator causing the processor to load the SMI timer causes the processor to:
- load the SMI timer in a chipset.
Dependencies are inferred from the claim text.