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OwnerEric J. Stotzer, Michael D. Asalinventors
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A program memory controller unit includes apparatus for the execution of a software pipeline procedure in response to a predetermined instruction. The apparatus provides a prolog, a kernel, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline procedure can be terminated early. A second software procedure can be initiated prior to the completion of first software procedure. The apparatus can execute an inner nested loop of a nested loop instruction set as a software pipeline procedure. The inner nested loop instruction set is stored in a buffer memory unit during the execution of the outer nested loop instruction set. The epilog of the inner nested loop instruction set can overlap the execution of the outer loop instruction set and the execution of the prolog of the next inner nested loop procedure.
A multiple execution unit processor, the processor comprising:
A method of executing a nested-loop set of instruction stages, the execution including the execution of outer loop instruction stages a first plurality of times, the execution of the nested loop of instructions including execution of inner loop instruction stages a second plurality of times for each execution of the outer loop of instruction stages, the method comprising:
The method as recited in claim 9 further comprising:
A digital signal processor, the processor executing nested loop instructions stages, the nested loop instruction stages including a set of outer instruction stages and a set of inner instruction stages, the processor comprising:
Dependencies are inferred from the claim text.