Load/move and duplicate instructions for a processor
AssigneeIntel Corporation
InventorPatrice Roussel
Life of this patent
Estimating the term…
Abstract
A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.
Claims58
A computer instruction comprises:
- a move and duplicate instruction that causes a processor to load a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.
A method comprising:
- in a processor, loading a first portion of bits of a source into a first portion of a destination register;
- and
- duplicating the first portion of bits in a subsequent portion of the destination register.
A computer program product residing on a computer readable medium having instructions stored thereon which, when executed by the processor, cause the processor to:
- load a first portion of bits of a source into a first portion of a destination register;
- and
- duplicate the first portion of bits in a subsequent portion of the destination register.
A computer instruction comprises:
- a move one double floating point and duplicate instruction that causes a processor to load 64-bits of a source and return the 64-bits in a lower half of a destination and a upper half of a destination.
A method executed in a processor comprising:
- loading a first number N of bits from a source into a lower half of a 2N wide-bit destination register and in a upper half of the 2N-bit wide destination register.
A computer program product residing on a computer readable medium having instructions stored thereon which, when executed by the processor, cause the processor to:
- load 64-bits from a source in a lower half of a 128-bit destination register and in an upper half of the 128-bit destination register.
A computer instruction comprises:
- a move packed single floating point high and duplicate instruction that causes a processor to load bits [127-0] of a source and return bits [63-32] of the source in bits [31-0] of a 128-bit destination register, bits [63-32] of the source in bits [63-32] of the destination register, bits [127-96] of the source in bits [95-64] of the destination register and bits [127-96] of the source in bits [127-96] of the destination register.
A method executed in a processor comprising:
- accessing bits [127-0] of a source;
- and
- returning bits [63-32] of the source in bits [31-0] and bits [63-32] of the destination register;
- and
- bits [127-96] of the source in bits [95-64] and bits [127-96] of the destination register.
A computer program product residing on a computer readable medium having instructions stored thereon which, when executed by the processor, cause the processor to:
- load bits [127-0] of a source;
- return bits [63-32] of the source in bits [31-0] of a 128-bit destination register;
- return bits [63-32] of the source in bits [63-32] of the destination register;
- return bits [127-96] of the source in bits [95-64] of the destination register;
- and
- return bits [127-96] of the source in bits [127-96] of the destination register.
A computer instruction comprises:
- a move a packed single floating point low and duplicate instruction that causes a processor to load bits [127-0] of a source and return bits [31-0] of the source in bits [31-0] of a 128-bit destination register, bits [31-0] of the source in bits [63-32] of the destination register, bits [95-64] of the source in bits [95-64] of the destination register and bits [95-64] of the source in bits [127-96] of the destination register.
A method comprising:
- in a processor, loading bits [127-0] of a source;
- returning bits [31-0] of the source in bits [31-0] of a 128-bit destination register;
- returning bits [31-0] of the source in bits [63-32] of the destination register;
- returning bits [95-64] of the source in bits [95-64] of the destination register;
- and
- returning bits [95-64] of the source in bits [127-96] of the destination register.
A computer program product residing on a computer readable medium having instructions stored thereon which, when executed by the processor, cause the processor to:
- load bits [127-0] of a source;
- return bits [31-0] of the source in bits [31-0] of a 128-bit destination register;
- return bits [31-0] of the source in bits [63-32] of the destination register;
- return bits [95-64] of the source in bits [95-64] of the destination register;
- and
- return bits [95-64] of the source in bits [127-96] of the destination register.
Dependencies are inferred from the claim text.