Apparatus and method for a software pipeline loop procedure in a digital signal processor
OwnerEric J. Stotzer, Steven D. Krueger +1inventors
InventorsEric J. Stotzer, Steven D. Krueger, Timothy Anderson
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Abstract
A program memory controller unit includes apparatus for the execution of a software pipeline procedure in response to a predetermined instruction. The apparatus provides a prolog, a kernel, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline loop procedure can be terminated early. A second software pipeline loop procedure can be initiated prior to the completion of first software pipeline loop procedure.
Claims14
A multiple execution unit processor, the processor comprising:
- a memory unit storing a plurality of instruction stages, each instruction stage including at least one execution packet;
- a buffer storage unit for storing the instruction stages;
- a dispatch unit for directing each instruction of an execution packet applied thereto to an preselected execution unit;
- and
- a program memory control unit for retrieving an execution packet from the memory unit, the program memory unit having a first state wherein an execution instruction from the memory unit is applied to the dispatch unit and to the buffer storage unit, the instruction stage applied to the execution unit being stored therein, wherein in the first prolog state the retrieved execution packet and any execution packet stored in the buffer storage unit and corresponding to the retrieved execution packet are applied to the dispatch unit simultaneously, the program control memory unit having a second kernel state wherein the corresponding execution packets stored in the buffer storage unit are simultaneously applied to the dispatch unit, the program control memory unit having a third epilog state wherein the earliest stored execution packet in the buffer storage unit is eliminated after each application to the dispatch unit.
The processor as recited in 1 wherein an instruction identified by a mask instruction in an execution packet in the first state can be applied to dispatch unit only once.
The method of executing a software pipeline loop, the method comprising:
- in a first prolog state of a processor, applying to a selected decode/execution machine while simultaneously storing in a buffer unit each of a preselected set of instruction stages, each instruction stage having at least one execution packet;
- after the last of the preselected set of instruction stages is stored in the buffer unit, transitioning to a second kernel state of the processor wherein the set of instruction stages stored in the buffer unit are simultaneously applied to the selected decode/buffer units;
- after the set of instruction stages has been applied to the decoder/execution units a predetermined number of times, entering a third epilog state of the processor wherein the earliest stored instruction stage in the buffer unit is removed from a subsequent application of the stored instruction set to the decode/execution unit;
- and
- in response to a preselected condition during the first stage, transitioning the processor to a fourth state, the fourth over-lap state simultaneously storing the next instruction stage in the set of instruction stages while removing the remaining earliest filed instruction stage for the buffer unit.
In a program memory controller unit, a method of processing an instruction in an SPL_PROLOG state, the method comprising:
- in response to absence of a mask instruction in an execution packet, storing the execution packet in a dispatch buffer unit and applying the execution packet to a dispatch crossbar unit;
- and
- in response to the presence of a mask instruction identifying at least one preselected instruction in an execution packet, applying the at least one instruction only to the dispatch crossbar unit.
Dependencies are inferred from the claim text.