Apparatus and method for processing an interrupt in a software pipeline loop procedure in a digital signal processor

A method for preparing for the servicing of an interrupt signal by a program memory controller unit when the program memory controller unit is implementing a software pipeline procedure, the method comprising:

• when the program memory controller unit is in a prolog state, completing the filling of a buffer storage unit with instruction stages;
• when the prolog state is complete, freezing the predicate register, restoring and freezing the initial address of the instruction set for the software pipeline procedure in the program counter;
• entering a special epilog state for draining the instruction stages in the buffer storage unit without parallel processing of the instruction set;
• and
• when the special epilog state is complete, providing an indicia that the program memory controller unit is ready for the interrupt identified by the interrupt signal to be processed.

A data processing unit comprising:

• a central processing unit, the central processing unit including a plurality of execution units;
• at least one memory unit storing a multiplicity of execution packets;
• a data memory controller unit;
• a buffer storage unit for storing a plurality of execution packets;
• a dispatch unit coupled to the buffer storage unit for directing each instruction stage applied to the dispatch unit to an preselected execution unit;
• and
• a program memory control unit having a program counter, the program memory controller unit retrieving an execution packet identified by the program counter from the at least one memory unit, the program memory unit having a first state wherein an execution packet from the memory unit is applied to the dispatch unit and to the buffer storage unit, the execution packet being applied to the dispatch buffer unit being stored therein, wherein in the first state the retrieved execution packet and any execution packet stored in the buffer storage unit are applied to the dispatch unit simultaneously, the program control memory unit having a second state wherein corresponding execution packets in sequential instruction packets in the buffer storage unit are simultaneously applied to the dispatch unit, the program memory controller unit having a third state wherein after each earliest stored execution packet in the buffer storage unit is eliminated after application to the dispatch crossbar unit, the program memory controller unit having a fourth state for preparing the program memory controller unit to process an interrupt signal.